bindings/interrupt-controller/sifive%2Cplic-1.0.0.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11   SiFive SoCs and other RISC-V SoCs include an implementation of the
12   Platform-Level Interrupt Controller (PLIC) high-level specification in
13   the RISC-V Privileged Architecture specification. The PLIC connects all
14   external interrupts in the system to all hart contexts in the system, via
15   the external interrupt source in each hart.
18   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21   Each interrupt can be enabled on per-context basis. Any context can claim
29   The PLIC supports both edge-triggered and level-triggered interrupts. For
30   edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
36   RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40   contains a specific memory layout, which is documented in chapter 8 of the
41   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43   The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44   T-HEAD PLIC implementation requires setting a delegation bit to allow access
45   from S-mode. So add thead,c900-plic to distinguish them.
48   - Paul Walmsley  <paul.walmsley@sifive.com>
49   - Palmer Dabbelt <palmer@dabbelt.com>
54       - items:
55           - enum:
56               - renesas,r9a07g043-plic
57           - const: andestech,nceplic100
58       - items:
59           - enum:
60               - canaan,k210-plic
61               - sifive,fu540-c000-plic
62               - starfive,jh7100-plic
63               - starfive,jh7110-plic
64           - const: sifive,plic-1.0.0
65       - items:
66           - enum:
67               - allwinner,sun20i-d1-plic
68               - sophgo,cv1800b-plic
69               - sophgo,cv1812h-plic
70               - sophgo,sg2042-plic
71               - thead,th1520-plic
72           - const: thead,c900-plic
73       - items:
74           - const: sifive,plic-1.0.0
75           - const: riscv,plic0
82   '#address-cells':
85   '#interrupt-cells': true
87   interrupt-controller: true
89   interrupts-extended:
93       Specifies which contexts are connected to the PLIC, with "-1" specifying
95       riscv,cpu-intc node, which has a riscv node as parent.
100       Specifies how many external interrupts are supported by this controller.
104   power-domains: true
109   - compatible
110   - '#address-cells'
111   - '#interrupt-cells'
112   - interrupt-controller
113   - reg
114   - interrupts-extended
115   - riscv,ndev
118   - if:
123               - andestech,nceplic100
124               - thead,c900-plic
128         '#interrupt-cells':
133         '#interrupt-cells':
136   - if:
140             const: renesas,r9a07g043-plic
147         power-domains:
154         - clocks
155         - power-domains
156         - resets
161   - |
162     plic: interrupt-controller@c000000 {
163       #address-cells = <0>;
164       #interrupt-cells = <1>;
165       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
166       interrupt-controller;
167       interrupts-extended = <&cpu0_intc 11>,