bindings/interrupt-controller/arm%2Cgic-v3.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10   - Marc Zyngier <maz@kernel.org>
15   Software Generated Interrupts (SGI), and Locality-specific Peripheral
19   - $ref: /schemas/interrupt-controller.yaml#
24       - items:
25           - enum:
26               - qcom,msm8996-gic-v3
27           - const: arm,gic-v3
28       - const: arm,gic-v3
30   interrupt-controller: true
32   "#address-cells":
34   "#size-cells":
39   "#interrupt-cells":
41       Specifies the number of cells needed to encode an interrupt source.
43       If the system requires describing PPI affinity, then the value must
46       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
50       The 2nd cell contains the interrupt number for the interrupt type.
51       SPI interrupts are in the range [0-987]. PPI interrupts are in the
52       range [0-15]. Extended SPI interrupts are in the range [0-1023].
53       Extended PPI interrupts are in the range [0-127].
61       interrupt is affine to. The interrupt must be a PPI, and the node
62       pointed must be a subnode of the "ppi-partitions" subnode. For
63       interrupt types other than PPI or PPIs that are not partitionned,
64       this cell must be zero. See the "ppi-partitions" node description
75       - GIC Distributor interface (GICD)
76       - GIC Redistributors (GICR), one range per redistributor region
77       - GIC CPU interface (GICC)
78       - GIC Hypervisor interface (GICH)
79       - GIC Virtual CPU interface (GICV)
83       ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
91       Interrupt source of the VGIC maintenance interrupt.
94   redistributor-stride:
102   "#redistributor-regions":
109   dma-noncoherent:
112       and cacheability attributes but are connected to a non-coherent
115   msi-controller:
117       Only present if the Message Based Interrupt functionality is
118       being exposed by the HW, and the mbi-ranges property present.
120   mbi-ranges:
125     $ref: /schemas/types.yaml#/definitions/uint32-matrix
130   mbi-alias:
135     $ref: /schemas/types.yaml#/definitions/uint32-array
140   ppi-partitions:
144       PPI affinity can be expressed as a single "ppi-partitions" node,
145       containing a set of sub-nodes.
147       "^interrupt-partition-[0-9]+$":
151           affinity:
152             $ref: /schemas/types.yaml#/definitions/phandle-array
160           - affinity
165   clock-names:
167       - const: aclk
169   power-domains:
175   mediatek,broken-save-restore-fw:
182   mbi-ranges: [ msi-controller ]
183   msi-controller: [ mbi-ranges ]
186   - compatible
187   - reg
190   "^gic-its@": false
191   "^interrupt-controller@[0-9a-f]+$": false
192   # msi-controller is preferred, but allow other names
193   "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
196       GICv3 has one or more Interrupt Translation Services (ITS) that are
200         const: arm,gic-v3-its
202       dma-noncoherent:
205           cacheability attributes but is connected to a non-coherent
208       msi-controller: true
210       "#msi-cells":
212           The single msi-cell is the DeviceID of the device which will generate
221       socionext,synquacer-pre-its:
224           address and size of the pre-ITS window.
225         $ref: /schemas/types.yaml#/definitions/uint32-array
231       - compatible
232       - msi-controller
233       - "#msi-cells"
234       - reg
241   - |
242     gic: interrupt-controller@2cf00000 {
243       compatible = "arm,gic-v3";
244       #interrupt-cells = <3>;
245       #address-cells = <1>;
246       #size-cells = <1>;
248       interrupt-controller;
256       msi-controller;
257       mbi-ranges = <256 128>;
259       msi-controller@2c200000 {
260         compatible = "arm,gic-v3-its";
261         msi-controller;
262         #msi-cells = <1>;
267   - |
268     interrupt-controller@2c010000 {
269       compatible = "arm,gic-v3";
270       #interrupt-cells = <4>;
271       #address-cells = <1>;
272       #size-cells = <1>;
274       interrupt-controller;
275       redistributor-stride = <0x0 0x40000>;  // 256kB stride
276       #redistributor-regions = <2>;
278             <0x2d000000 0x800000>,  // GICR 1: CPUs 0-31
279             <0x2e000000 0x800000>,  // GICR 2: CPUs 32-63
285       msi-controller@2c200000 {
286         compatible = "arm,gic-v3-its";
287         msi-controller;
288         #msi-cells = <1>;
292       msi-controller@2c400000 {
293         compatible = "arm,gic-v3-its";
294         msi-controller;
295         #msi-cells = <1>;
299       ppi-partitions {
300         part0: interrupt-partition-0 {
301           affinity = <&cpu0>, <&cpu2>;
304         part1: interrupt-partition-1 {
305           affinity = <&cpu1>, <&cpu3>;