Lines Matching +full:mdss +full:- +full:dsi +full:- +full:ctrl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8650 Display MDSS
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8650-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
42 const: qcom,sm8650-dpu
44 "^displayport-controller@[0-9a-f]+$":
48 const: qcom,sm8650-dp
50 "^dsi@[0-9a-f]+$":
55 - const: qcom,sm8650-dsi-ctrl
56 - const: qcom,mdss-dsi-ctrl
58 "^phy@[0-9a-f]+$":
62 const: qcom,sm8650-dsi-phy-4nm
65 - compatible
70 - |
71 #include <dt-bindings/clock/qcom,rpmh.h>
72 #include <dt-bindings/interrupt-controller/arm-gic.h>
73 #include <dt-bindings/power/qcom,rpmhpd.h>
75 display-subsystem@ae00000 {
76 compatible = "qcom,sm8650-mdss";
78 reg-names = "mdss";
82 power-domains = <&dispcc_gdsc>;
87 clock-names = "bus", "nrt_bus", "core";
90 interrupt-controller;
91 #interrupt-cells = <1>;
95 #address-cells = <1>;
96 #size-cells = <1>;
99 display-controller@ae01000 {
100 compatible = "qcom,sm8650-dpu";
103 reg-names = "mdp", "vbif";
110 clock-names = "nrt_bus",
116 assigned-clocks = <&dispcc_mdp_vsync_clk>;
117 assigned-clock-rates = <19200000>;
119 operating-points-v2 = <&mdp_opp_table>;
120 power-domains = <&rpmhpd RPMHPD_MMCX>;
122 interrupt-parent = <&mdss>;
126 #address-cells = <1>;
127 #size-cells = <0>;
132 remote-endpoint = <&dsi0_in>;
139 remote-endpoint = <&dsi1_in>;
144 mdp_opp_table: opp-table {
145 compatible = "operating-points-v2";
147 opp-200000000 {
148 opp-hz = /bits/ 64 <200000000>;
149 required-opps = <&rpmhpd_opp_low_svs>;
152 opp-325000000 {
153 opp-hz = /bits/ 64 <325000000>;
154 required-opps = <&rpmhpd_opp_svs>;
157 opp-375000000 {
158 opp-hz = /bits/ 64 <375000000>;
159 required-opps = <&rpmhpd_opp_svs_l1>;
162 opp-514000000 {
163 opp-hz = /bits/ 64 <514000000>;
164 required-opps = <&rpmhpd_opp_nom>;
169 dsi@ae94000 {
170 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
172 reg-names = "dsi_ctrl";
174 interrupt-parent = <&mdss>;
183 clock-names = "byte",
190 assigned-clocks = <&dispcc_byte_clk>,
192 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
194 operating-points-v2 = <&dsi_opp_table>;
195 power-domains = <&rpmhpd RPMHPD_MMCX>;
198 phy-names = "dsi";
200 #address-cells = <1>;
201 #size-cells = <0>;
204 #address-cells = <1>;
205 #size-cells = <0>;
210 remote-endpoint = <&dpu_intf1_out>;
221 dsi_opp_table: opp-table {
222 compatible = "operating-points-v2";
224 opp-187500000 {
225 opp-hz = /bits/ 64 <187500000>;
226 required-opps = <&rpmhpd_opp_low_svs>;
229 opp-300000000 {
230 opp-hz = /bits/ 64 <300000000>;
231 required-opps = <&rpmhpd_opp_svs>;
234 opp-358000000 {
235 opp-hz = /bits/ 64 <358000000>;
236 required-opps = <&rpmhpd_opp_svs_l1>;
242 compatible = "qcom,sm8650-dsi-phy-4nm";
246 reg-names = "dsi_phy",
250 #clock-cells = <1>;
251 #phy-cells = <0>;
255 clock-names = "iface", "ref";
258 dsi@ae96000 {
259 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
261 reg-names = "dsi_ctrl";
263 interrupt-parent = <&mdss>;
272 clock-names = "byte",
279 assigned-clocks = <&dispcc_byte_clk>,
281 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
283 operating-points-v2 = <&dsi_opp_table>;
284 power-domains = <&rpmhpd RPMHPD_MMCX>;
287 phy-names = "dsi";
289 #address-cells = <1>;
290 #size-cells = <0>;
293 #address-cells = <1>;
294 #size-cells = <0>;
299 remote-endpoint = <&dpu_intf2_out>;
312 compatible = "qcom,sm8650-dsi-phy-4nm";
316 reg-names = "dsi_phy",
320 #clock-cells = <1>;
321 #phy-cells = <0>;
325 clock-names = "iface", "ref";