Lines Matching +full:mdss +full:- +full:dsi +full:- +full:ctrl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8150 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SM8150 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
28 - description: Display sf axi clock
29 - description: Display core clock
31 clock-names:
33 - const: iface
34 - const: bus
35 - const: nrt_bus
36 - const: core
44 interconnect-names:
48 "^display-controller@[0-9a-f]+$":
54 const: qcom,sm8150-dpu
56 "^dsi@[0-9a-f]+$":
63 - const: qcom,sm8150-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl
66 "^phy@[0-9a-f]+$":
72 const: qcom,dsi-phy-7nm-8150
77 - |
78 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
79 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/interconnect/qcom,sm8150.h>
83 #include <dt-bindings/power/qcom-rpmpd.h>
85 display-subsystem@ae00000 {
86 compatible = "qcom,sm8150-mdss";
88 reg-names = "mdss";
92 interconnect-names = "mdp0-mem", "mdp1-mem";
94 power-domains = <&dispcc MDSS_GDSC>;
100 clock-names = "iface", "bus", "nrt_bus", "core";
103 interrupt-controller;
104 #interrupt-cells = <1>;
108 #address-cells = <1>;
109 #size-cells = <1>;
112 display-controller@ae01000 {
113 compatible = "qcom,sm8150-dpu";
116 reg-names = "mdp", "vbif";
122 clock-names = "iface", "bus", "core", "vsync";
124 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
125 assigned-clock-rates = <19200000>;
127 operating-points-v2 = <&mdp_opp_table>;
128 power-domains = <&rpmhpd SM8150_MMCX>;
130 interrupt-parent = <&mdss>;
134 #address-cells = <1>;
135 #size-cells = <0>;
140 remote-endpoint = <&dsi0_in>;
147 remote-endpoint = <&dsi1_in>;
152 mdp_opp_table: opp-table {
153 compatible = "operating-points-v2";
155 opp-171428571 {
156 opp-hz = /bits/ 64 <171428571>;
157 required-opps = <&rpmhpd_opp_low_svs>;
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 required-opps = <&rpmhpd_opp_svs>;
165 opp-345000000 {
166 opp-hz = /bits/ 64 <345000000>;
167 required-opps = <&rpmhpd_opp_svs_l1>;
170 opp-460000000 {
171 opp-hz = /bits/ 64 <460000000>;
172 required-opps = <&rpmhpd_opp_nom>;
177 dsi@ae94000 {
178 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
180 reg-names = "dsi_ctrl";
182 interrupt-parent = <&mdss>;
191 clock-names = "byte",
198 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
200 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
202 operating-points-v2 = <&dsi_opp_table>;
203 power-domains = <&rpmhpd SM8150_MMCX>;
206 phy-names = "dsi";
208 #address-cells = <1>;
209 #size-cells = <0>;
212 #address-cells = <1>;
213 #size-cells = <0>;
218 remote-endpoint = <&dpu_intf1_out>;
229 dsi_opp_table: opp-table {
230 compatible = "operating-points-v2";
232 opp-187500000 {
233 opp-hz = /bits/ 64 <187500000>;
234 required-opps = <&rpmhpd_opp_low_svs>;
237 opp-300000000 {
238 opp-hz = /bits/ 64 <300000000>;
239 required-opps = <&rpmhpd_opp_svs>;
242 opp-358000000 {
243 opp-hz = /bits/ 64 <358000000>;
244 required-opps = <&rpmhpd_opp_svs_l1>;
250 compatible = "qcom,dsi-phy-7nm-8150";
254 reg-names = "dsi_phy",
258 #clock-cells = <1>;
259 #phy-cells = <0>;
263 clock-names = "iface", "ref";
264 vdds-supply = <&vreg_dsi_phy>;
267 dsi@ae96000 {
268 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
270 reg-names = "dsi_ctrl";
272 interrupt-parent = <&mdss>;
281 clock-names = "byte",
288 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
290 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
292 operating-points-v2 = <&dsi_opp_table>;
293 power-domains = <&rpmhpd SM8150_MMCX>;
296 phy-names = "dsi";
298 #address-cells = <1>;
299 #size-cells = <0>;
302 #address-cells = <1>;
303 #size-cells = <0>;
308 remote-endpoint = <&dpu_intf2_out>;
321 compatible = "qcom,dsi-phy-7nm-8150";
325 reg-names = "dsi_phy",
329 #clock-cells = <1>;
330 #phy-cells = <0>;
334 clock-names = "iface", "ref";
335 vdds-supply = <&vreg_dsi_phy>;