display/mediatek/mediatek%2Csplit.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display split
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
14   Mediatek display split, namely SPLIT, is used to split stream to two
16   SPLIT device node must be siblings to the central MMSYS_CONFIG node.
24       - enum:
25           - mediatek,mt8173-disp-split
26           - mediatek,mt8195-mdp3-split
27       - items:
28           - const: mediatek,mt6795-disp-split
29           - const: mediatek,mt8173-disp-split
37   power-domains:
40       Documentation/devicetree/bindings/power/power-domain.yaml for details.
42   mediatek,gce-client-reg:
47       include/dt-bindings/gce/<chip>-gce.h of each chips.
48     $ref: /schemas/types.yaml#/definitions/phandle-array
51         - description: phandle of GCE
52         - description: GCE subsys id
53         - description: register offset
54         - description: register size
59       - description: SPLIT Clock
62   - compatible
63   - reg
64   - power-domains
65   - clocks
68   - if:
72             const: mediatek,mt8195-mdp3-split
76         - mediatek,gce-client-reg
81   - |
82     #include <dt-bindings/clock/mt8173-clk.h>
83     #include <dt-bindings/power/mt8173-power.h>
86         #address-cells = <2>;
87         #size-cells = <2>;
89         split0: split@14018000 {
90             compatible = "mediatek,mt8173-disp-split";
92             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;