bindings/bus/qcom%2Cebi2.txt

4 external memory (such as NAND or other memory-mapped peripherals) whereas
13 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
21 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
24 CS0 GPIO134                     0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B)    0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B)    0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133                     0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132                     0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131                     0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
36 in the hardware, or what valid values exist. The current hypothesis is that
37 this is something just used on the FAST chip selects and that the SLOW
38 chip selects are understood fully. There is also a "byte device enable"
46 The XMEM registers are totally undocumented but could be partially decoded
51 - compatible: should be one of:
52   "qcom,msm8660-ebi2"
53   "qcom,apq8060-ebi2"
54 - #address-cells: should be <2>: the first cell is the chipselect,
55   the second cell is the offset inside the memory range
56 - #size-cells: should be <1>
57 - ranges: should be set to:
64 - reg: two ranges of registers: EBI2 config and XMEM config areas
65 - reg-names: should be "ebi2", "xmem"
66 - clocks: two clocks, EBI_2X and EBI
67 - clock-names: should be "ebi2x", "ebi2"
70 - Nodes inside the EBI2 will be considered device nodes.
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
78   drive the data bus after OE is de-asserted, in order to avoid contention on
79   the data bus. They are inserted when reading one CS and switching to another
80   CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
81   value is actually 1, so a value of 0 will still yield 1 recovery cycle.
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
83   inserted after every write minimum 1. The data out is driven from the time
84   WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
96 - qcom,xmem-address-hold-enable: this is a boolean property stating that we
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
100   assertion, with respect to the cycle where ADV (address valid) is asserted.
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
103   read transfer. For a single read transfer this will be the time from CS
110 	compatible = "qcom,apq8060-ebi2";
111 	#address-cells = <2>;
112 	#size-cells = <1>;
120 	reg-names = "ebi2", "xmem";
122 	clock-names = "ebi2x", "ebi2";
124 	pinctrl-names = "default";
125 	pinctrl-0 = <&foo_ebi2_pins>;
127 	foo-ebi2@2,0 {
131 		qcom,xmem-recovery-cycles = <0>;
132 		qcom,xmem-write-hold-cycles = <3>;
133 		qcom,xmem-write-delta-cycles = <31>;
134 		qcom,xmem-read-delta-cycles = <28>;
135 		qcom,xmem-write-wait-cycles = <9>;
136 		qcom,xmem-read-wait-cycles = <9>;