arch/x86/buslock.rst

1 .. SPDX-License-Identifier: GPL-2.0
10 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
11           - Tony Luck <tony.luck@intel.com>
16 A split lock is any atomic operation whose operand crosses two cache lines.
17 Since the operand spans two cache lines and the operation must be atomic,
21 memory or any locked access to non-WB memory. This is typically thousands of
22 cycles slower than an atomic operation within a cache line. It also disrupts
32 --------------------------------------
35 Alignment Check (#AC) exception when a split lock operation is attempted.
38 ------------------------------------
50 +------------------+----------------------------+-----------------------+
52 +------------------+----------------------------+-----------------------+
54 +------------------+----------------------------+-----------------------+
55 |warn		   |Kernel OOPs			|Warn once per task and |
56 |(default)	   |Warn once per task, add a	|and continues to run.  |
66 +------------------+----------------------------+-----------------------+
71 +------------------+----------------------------+-----------------------+
73 |(0 < N <= 1000)   |				|N bus locks per second	|
76 +------------------+----------------------------+-----------------------+
100 ---
107 ----
113 -----
118 ---------
121 allows a bus lock rate up to N bus locks per second. When the bus lock rate