arch/powerpc/elf_hwcaps.rst

11 ---------------
46 -------------
56 -------------
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
74     32-bit CPU
77     64-bit CPU (userspace may be running in 32-bit mode).
104     Embedded Floating Point single precision operations are available.
107     Embedded Floating Point double precision operations are available.
166     The processor supports architected PMU events in the range 0xE0-0xFF.
169     The processor supports true little-endian mode.
172     The processor supports "PowerPC Little-Endian", that uses address
173     munging to make storage access appear to be little-endian, but the
178 ----------------------------------
205     Documentation/arch/powerpc/syscall64-abi.rst
212     IEEE 128-bit binary floating point is supported with VSX
213     quad-precision instructions and data types.
220     Documentation/arch/powerpc/syscall64-abi.rst.