arch/powerpc/dexcr.rst

1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 DEXCR (Dynamic Execution Control Register)
11 PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic
13 branch target prediction) and enabling return-oriented programming (ROP)
16 The execution control is exposed in hardware as up to 32 bits ('aspects') in
22     A privileged SPR that can control aspects for userspace and kernel space
24     A hypervisor-privileged SPR that can control aspects for the hypervisor and
27     An optional ultravisor-privileged SPR that can control aspects for the ultravisor.
30 provides a non-privileged read-only view of the userspace DEXCR aspects.
31 There is also an SPR that provides a read-only view of the hypervisor enforced
39 The DEXCR is currently unconfigurable. All threads are run with the
49 bits of both registers (corresponding to the non-userspace bits) are masked off.
58 key (potentially all threads from the same parent that have not run ``exec()``).