Lines Matching +full:model +full:- +full:dependent
18 model. To aid understanding, a minimal description of relevant programmer's
19 model features for SVE is included in Appendix A.
23 -----------
26 tracked per-thread.
34 instructions and registers, and the Linux-specific system interfaces
61 cpu-feature-registers.txt for details.
79 an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
84 Beware that on big-endian systems this results in a different byte order than
85 for the FPSIMD V-registers, which are stored as single host-endian 128-bit
86 values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
91 -----------------------------
98 * Vector length (VL) = size of a Z-register in bytes
100 * Vector quadwords (VQ) = size of a Z-register in units of 128 bits
106 is used. This is consistent with the meaning of the "VL" pseudo-register in
111 -------------------------
122 assumptions about this. The kernel behaviour may vary on a case-by-case
136 -------------------
158 * If the registers are present, the remainder of the record has a vl-dependent
162 * Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
173 -----------------
179 then the SVE registers/bits become non-live and take unspecified values.
201 --------------------
247 to be applied at the next execve() by the thread (dependent on whether
274 The following flag may be OR-ed into the result:
292 ---------------------
297 non-streaming mode SVE registers.
300 the target is in the appropriate streaming or non-streaming mode and is
337 non-live (SETREGSET).
359 ... OR-ed with zero or more of the following flags, which have the same
414 ---------------------------
422 --------------------------------
457 --------------------------------
475 Appendix A. SVE programmer's model (informative)
479 ARMv8-A programmer's model that are relevant to this document.
485 ---------------
489 * 32 8VL-bit vector registers Z0..Z31
490 For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
495 * 16 VL-bit predicate registers P0..P15
497 * 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
499 * a VL "pseudo-register" that determines the size of each vector register
514 * FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
516 floating-point operations::
518 8VL-1 128 0 bit index
519 +---- //// -----------------+
529 +---- //// -----------------+
531 VL-1 0 +-------+
532 +---- //// --+ FPSR | |
533 P0 | | +-------+
535 P15 | | +-------+
536 +---- //// --+
537 FFR | | +-----+
538 +---- //// --+ VL | |
539 +-----+
541 (*) callee-save:
542 This only applies to bits [63:0] of Z-/V-registers.
543 FPCR contains callee-save and caller-save bits. See [4] for details.
547 -----------------------------
549 The ARMv8-A base procedure call standard is extended as follows with respect to
552 * All SVE register bits that are not shared with FP/SIMD are caller-save.
554 * Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
556 This follows from the way these bits are mapped to V8..V15, which are caller-
560 Appendix B. ARMv8-A FP/SIMD programmer's model
568 ARMv8-A defines the following floating-point / SIMD register state:
570 * 32 128-bit vector registers V0..V31
571 * 2 32-bit status/control registers FPSR, FPCR
576 +---------------+
586 +---------------+
589 +-------+
591 +-------+
593 +-------+
595 (*) callee-save:
596 This only applies to bits [63:0] of V-registers.
597 FPCR contains a mixture of callee-save and caller-save bits.
609 [3] Documentation/arch/arm64/cpu-feature-registers.rst
614 Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
616 [5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst