arch/arm64/memory.rst

12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
21 User addresses have bits 63:48 set to 0 while the kernel addresses have
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32   -----------------------------------------------------------------------
46 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
49   -----------------------------------------------------------------------
65   +--------+--------+--------+--------+--------+--------+--------+--------+
66   |63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
67   +--------+--------+--------+--------+--------+--------+--------+--------+
70    |                 |         |         |         |   [11:0]  in-page offset
71    |                 |         |         |         +-> [20:12] L3 index
72    |                 |         |         +-----------> [29:21] L2 index
73    |                 |         +---------------------> [38:30] L1 index
74    |                 +-------------------------------> [47:39] L0 index
75    +-------------------------------------------------> [63] TTBR0/1
80   +--------+--------+--------+--------+--------+--------+--------+--------+
81   |63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
82   +--------+--------+--------+--------+--------+--------+--------+--------+
85    |                 |    |               |            [15:0]  in-page offset
86    |                 |    |               +----------> [28:16] L3 index
87    |                 |    +--------------------------> [41:29] L2 index
88    |                 +-------------------------------> [47:42] L1 index (48-bit)
89    |                                                   [51:42] L1 index (52-bit)
90    +-------------------------------------------------> [63] TTBR0/1
103 52-bit VA support in the kernel
104 -------------------------------
105 If the ARMv8.2-LVA optional feature is present, and we are running
106 with a 64KB page size; then it is possible to use 52-bits of address
108 binary that supports 52-bit must also be able to fall back to 48-bit
112 higher addresses such that they are invariant to 48/52-bit VAs. Due
115 kernel VA space for both 48/52-bit. (Switching from 48-bit to 52-bit,
120 is kept constant at 0xFFF0000000000000 (corresponding to 52-bit),
125 As a single binary will need to support both 48-bit and 52-bit VA
126 spaces, the VMEMMAP must be sized large enough for 52-bit VAs and
144 52-bit userspace VAs
145 --------------------
147 VA space maximum size of 48-bits, the kernel will, by default,
148 return virtual addresses to userspace from a 48-bit range.
150 Software can "opt-in" to receiving VAs from a 52-bit space by
151 specifying an mmap hint parameter that is larger than 48-bit.
155 .. code-block:: c
160 from a 52-bit space by enabling the following kernel config options:
162 .. code-block:: sh