admin-guide/perf/hisi-pcie-pmu.rst

8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
38   ------------------------------------------
40   $# perf stat -e hisi_pcie0_core0/rx_mwr_latency/
41   $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt/
42   $# perf stat -g -e hisi_pcie0_core0/rx_mwr_latency/ -e hisi_pcie0_core0/rx_mwr_cnt/
48 --------------
53    Ports or downstream target Endpoint. PCIe PMU driver support "port" and
57    - port
59      "port" filter can be used in all PCIe PMU events, target Root Port can be
60      selected by configuring the 16-bits-bitmap "port". Multi ports can be
61      selected for AP-layer-events, and only one port can be selected for
62      TL/DL-layer-events.
64      For example, if target Root Port is 0000:00:00.0 (x8 lanes), bit0 of
65      bitmap should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4
66      lanes), bit8 is set, port=0x100; if these two Root Ports are both
67      monitored, port=0x101.
71        $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
73    - bdf
83        $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,bdf=0x3900/ sleep 5
98      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,trig_len=0x4,trig_mode=1/ sleep 5
112      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,thr_len=0x4,thr_mode=1/ sleep 5
119    - 2'b00: Reserved (Do not use this since the behaviour is undefined)
120    - 2'b01: Bandwidth of TLP payloads
121    - 2'b10: Bandwidth of TLP headers
122    - 2'b11: Bandwidth of both TLP payloads and headers
130      $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,len_mode=0x1/ sleep 5