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1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
45 int isa_dma_bridge_buggy;
49 int pci_pci_problems;
52 unsigned int pci_pm_d3hot_delay;
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
85 unsigned int upper; in pci_dev_d3_sleep()
97 return dev->reset_methods[0] != 0; in pci_reset_supported()
101 int pci_domains_supported = 1;
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
141 * The default CLS is used if arch didn't set CLS explicitly and not
144 * measured in 32-bit words, not bytes.
153 unsigned int pcibios_max_latency = 255;
175 static int __init pcie_port_pm_setup(char *str) in pcie_port_pm_setup()
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
190 * including the given PCI bus and its list of child PCI buses.
197 max = bus->busn_res.end; in pci_bus_max_busnr()
198 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
211 * Returns error bits set in PCI_STATUS and clears them.
213 int pci_status_get_and_clear_errors(struct pci_dev *pdev) in pci_status_get_and_clear_errors()
216 int ret; in pci_status_get_and_clear_errors()
220 return -EIO; in pci_status_get_and_clear_errors()
231 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar, in __pci_ioremap_resource()
234 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
235 resource_size_t start = res->start; in __pci_ioremap_resource()
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
252 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) in pci_ioremap_bar()
258 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) in pci_ioremap_wc_bar()
266 * pci_dev_str_match_path - test if a path string matches a device
277 * A path for a device can be obtained using 'lspci -t'. Using a path
279 * device and function address.
281 * Returns 1 if the string matches the device, 0 if it does not and
284 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, in pci_dev_str_match_path()
287 int ret; in pci_dev_str_match_path()
288 unsigned int seg, bus, slot, func; in pci_dev_str_match_path()
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
296 return -ENOMEM; in pci_dev_str_match_path()
304 ret = -EINVAL; in pci_dev_str_match_path()
308 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
317 * and so on. in pci_dev_str_match_path()
334 ret = -EINVAL; in pci_dev_str_match_path()
339 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
340 bus == dev->bus->number && in pci_dev_str_match_path()
341 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
349 * pci_dev_str_match - test if a string matches a device
366 * through the use of 'lspci -t'.
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
372 * legacy reasons and convenience so users don't have to specify
375 * Returns 1 if the string matches the device, 0 if it does not and
378 static int pci_dev_str_match(struct pci_dev *dev, const char *p, in pci_dev_str_match()
381 int ret; in pci_dev_str_match()
382 int count; in pci_dev_str_match()
393 return -EINVAL; in pci_dev_str_match()
401 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
402 (!device || device == dev->device) && in pci_dev_str_match()
404 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
406 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
428 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap_ttl()
429 u8 pos, int cap, int *ttl) in __pci_find_next_cap_ttl()
436 while ((*ttl)--) { in __pci_find_next_cap_ttl()
452 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap()
453 u8 pos, int cap) in __pci_find_next_cap()
455 int ttl = PCI_FIND_CAP_TTL; in __pci_find_next_cap()
460 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) in pci_find_next_capability()
462 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
468 unsigned int devfn, u8 hdr_type) in __pci_bus_find_cap_start()
488 * pci_find_capability - query for devices' capabilities
495 * support it. Possible values for @cap include:
503 * %PCI_CAP_ID_PCIX PCI-X
506 u8 pci_find_capability(struct pci_dev *dev, int cap) in pci_find_capability()
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
519 * pci_bus_find_capability - query for devices' capabilities
531 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) in pci_bus_find_capability()
546 * pci_find_next_ext_capability - Find an extended capability
554 * vendor-specific capability, and this provides a way to find them all.
556 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) in pci_find_next_ext_capability()
559 int ttl; in pci_find_next_ext_capability()
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
576 * cap version and next pointer all being 0. in pci_find_next_ext_capability()
581 while (ttl-- > 0) { in pci_find_next_ext_capability()
598 * pci_find_ext_capability - Find an extended capability
604 * not support it. Possible values for @cap include:
611 u16 pci_find_ext_capability(struct pci_dev *dev, int cap) in pci_find_ext_capability()
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
621 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
630 int pos; in pci_get_dsn()
639 * the lower half, and the second dword is the upper half. in pci_get_dsn()
651 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) in __pci_find_next_ht_cap()
653 int rc, ttl = PCI_FIND_CAP_TTL; in __pci_find_next_ht_cap()
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
692 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) in pci_find_next_ht_capability()
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
709 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) in pci_find_ht_capability()
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
725 * @cap: Vendor-specific capability ID
731 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) in pci_find_vsec_capability()
736 if (vendor != dev->vendor) in pci_find_vsec_capability()
752 * pci_find_dvsec_capability - Find DVSEC for vendor
755 * @dvsec: Designated Vendor-specific capability ID
757 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
762 int pos; in pci_find_dvsec_capability()
784 * pci_find_parent_resource - return resource region of parent bus of given
795 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
807 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
808 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
813 * be both a positively-decoded aperture and a in pci_find_parent_resource()
814 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
815 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
827 * pci_find_resource - Return matching PCI device resource
831 * Goes over standard PCI resources (BARs) and checks if the given resource
837 int i; in pci_find_resource()
840 struct resource *r = &dev->resource[i]; in pci_find_resource()
842 if (r->start && resource_contains(r, res)) in pci_find_resource()
851 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
858 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) in pci_wait_for_pending()
860 int i; in pci_wait_for_pending()
866 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
876 static int pci_acs_enable;
879 * pci_request_acs - ask for ACS to be enabled if supported
889 * pci_disable_acs_redir - disable ACS redirect capabilities
896 int ret = 0; in pci_disable_acs_redir()
898 int pos; in pci_disable_acs_redir()
930 pos = dev->acs_cap; in pci_disable_acs_redir()
947 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
952 int pos; in pci_std_enable_acs()
956 pos = dev->acs_cap; in pci_std_enable_acs()
975 /* Enable Translation Blocking for external devices and noats */ in pci_std_enable_acs()
976 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
983 * pci_enable_acs - enable ACS if hardware support it
1008 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1011 * Restore the BAR values for a given device, so as to make it
1016 int i; in pci_restore_bars()
1030 static inline int platform_pci_set_power_state(struct pci_dev *dev, in platform_pci_set_power_state()
1061 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) in platform_pci_set_wakeup()
1086 * pci_update_current_state - Read power state of given device and cache it
1100 dev->current_state = PCI_D3cold; in pci_update_current_state()
1101 } else if (dev->pm_cap) { in pci_update_current_state()
1104 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1106 dev->current_state = PCI_D3cold; in pci_update_current_state()
1109 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1111 dev->current_state = state; in pci_update_current_state()
1116 * pci_refresh_power_state - Refresh the given device's power state data
1119 * Ask the platform to refresh the devices power state information and invoke
1125 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1129 * pci_platform_power_transition - Use platform to change device power state
1133 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) in pci_platform_power_transition()
1135 int error; in pci_platform_power_transition()
1140 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1141 dev->current_state = PCI_D0; in pci_platform_power_transition()
1147 static int pci_resume_one(struct pci_dev *pci_dev, void *ign) in pci_resume_one()
1149 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1154 * pci_resume_bus - Walk given bus and runtime resume devices on it
1163 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) in pci_dev_wait()
1165 int delay = 1; in pci_dev_wait()
1180 * the read (except when CRS SV is enabled and the read was for the in pci_dev_wait()
1183 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1196 delay - 1, reset_type); in pci_dev_wait()
1197 return -ENOTTY; in pci_dev_wait()
1209 delay - 1, reset_type); in pci_dev_wait()
1217 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1224 * pci_power_up - Put the given device into D0
1232 * put the device in D0 via non-PCI means.
1234 int pci_power_up(struct pci_dev *dev) in pci_power_up()
1242 if (!dev->pm_cap) { in pci_power_up()
1245 dev->current_state = PCI_D0; in pci_power_up()
1247 dev->current_state = state; in pci_power_up()
1249 return -EIO; in pci_power_up()
1252 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1255 pci_power_name(dev->current_state)); in pci_power_up()
1256 dev->current_state = PCI_D3cold; in pci_power_up()
1257 return -EIO; in pci_power_up()
1262 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1270 * PME_En, and sets PowerState to 0. in pci_power_up()
1272 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1281 dev->current_state = PCI_D0; in pci_power_up()
1289 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1293 * to confirm the state change, restore its BARs if they might be lost and
1300 static int pci_set_full_power_state(struct pci_dev *dev) in pci_set_full_power_state()
1303 int ret; in pci_set_full_power_state()
1307 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1313 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1314 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1315 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1317 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1324 * For example, at least some versions of the 3c905B and the in pci_set_full_power_state()
1339 * __pci_dev_set_current_state - Set current state of a PCI device
1343 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) in __pci_dev_set_current_state()
1347 dev->current_state = state; in __pci_dev_set_current_state()
1352 * pci_bus_set_current_state - Walk given bus and set current state of devices
1363 * pci_set_low_power_state - Put a PCI device into a low-power state.
1367 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1370 * -EINVAL if the requested state is invalid.
1371 * -EIO if device does not support PCI PM or its PM capabilities register has a
1376 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_low_power_state()
1380 if (!dev->pm_cap) in pci_set_low_power_state()
1381 return -EIO; in pci_set_low_power_state()
1385 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1389 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1391 pci_power_name(dev->current_state), in pci_set_low_power_state()
1393 return -EINVAL; in pci_set_low_power_state()
1397 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1398 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1399 return -EIO; in pci_set_low_power_state()
1401 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1404 pci_power_name(dev->current_state), in pci_set_low_power_state()
1406 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1407 return -EIO; in pci_set_low_power_state()
1414 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1422 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1423 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1424 if (dev->current_state != state) in pci_set_low_power_state()
1426 pci_power_name(dev->current_state), in pci_set_low_power_state()
1433 * pci_set_power_state - Set the power state of a PCI device
1437 * Transition a device to a new power state, using the platform firmware and/or
1441 * -EINVAL if the requested state is invalid.
1442 * -EIO if device does not support PCI PM or its PM capabilities register has a
1444 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1449 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_power_state()
1451 int error; in pci_set_power_state()
1469 if (dev->current_state == state) in pci_set_power_state()
1479 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in pci_set_power_state()
1493 if (dev->current_state == PCI_D3cold) in pci_set_power_state()
1494 pci_bus_set_current_state(dev->subordinate, PCI_D3cold); in pci_set_power_state()
1513 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1514 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1530 static int pci_save_pcie_state(struct pci_dev *dev) in pci_save_pcie_state()
1532 int i = 0; in pci_save_pcie_state()
1542 return -ENOMEM; in pci_save_pcie_state()
1545 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1564 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1567 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1577 int i = 0; in pci_restore_pcie_state()
1587 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1592 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1602 static int pci_save_pcix_state(struct pci_dev *dev) in pci_save_pcix_state()
1604 int pos; in pci_save_pcix_state()
1614 return -ENOMEM; in pci_save_pcix_state()
1618 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1625 int i = 0, pos; in pci_restore_pcix_state()
1633 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1640 int ltr; in pci_save_ltr_state()
1658 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
1665 int ltr; in pci_restore_ltr_state()
1674 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
1679 * pci_save_state - save the PCI configuration space of a device before
1683 int pci_save_state(struct pci_dev *dev) in pci_save_state()
1685 int i; in pci_save_state()
1688 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1690 i * 4, dev->saved_config_space[i]); in pci_save_state()
1692 dev->state_saved = true; in pci_save_state()
1710 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, in pci_restore_config_dword()
1711 u32 saved_val, int retry, bool force) in pci_restore_config_dword()
1720 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1723 if (retry-- <= 0) in pci_restore_config_dword()
1735 int start, int end, int retry, in pci_restore_config_space_range()
1738 int index; in pci_restore_config_space_range()
1740 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1742 pdev->saved_config_space[index], in pci_restore_config_space_range()
1748 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1753 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1770 unsigned int pos, nbars, i; in pci_restore_rebar_state()
1783 int bar_idx, size; in pci_restore_rebar_state()
1787 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1796 * pci_restore_state - Restore the saved state of a PCI device
1801 if (!dev->state_saved) in pci_restore_state()
1827 /* Restore ACS and IOV configuration state */ in pci_restore_state()
1831 dev->state_saved = false; in pci_restore_state()
1841 * pci_store_saved_state - Allocate and return an opaque struct containing
1854 if (!dev->state_saved) in pci_store_saved_state()
1859 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1860 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1866 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1867 sizeof(state->config_space)); in pci_store_saved_state()
1869 cap = state->cap; in pci_store_saved_state()
1870 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1871 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1872 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1882 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1886 int pci_load_saved_state(struct pci_dev *dev, in pci_load_saved_state()
1891 dev->state_saved = false; in pci_load_saved_state()
1896 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1897 sizeof(state->config_space)); in pci_load_saved_state()
1899 cap = state->cap; in pci_load_saved_state()
1900 while (cap->size) { in pci_load_saved_state()
1903 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1904 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
1905 return -EINVAL; in pci_load_saved_state()
1907 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
1909 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
1912 dev->state_saved = true; in pci_load_saved_state()
1918 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1919 * and free the memory allocated for it.
1923 int pci_load_and_free_saved_state(struct pci_dev *dev, in pci_load_and_free_saved_state()
1926 int ret = pci_load_saved_state(dev, *state); in pci_load_and_free_saved_state()
1933 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) in pcibios_enable_device()
1938 static int do_pci_enable_device(struct pci_dev *dev, int bars) in do_pci_enable_device()
1940 int err; in do_pci_enable_device()
1946 if (err < 0 && err != -EIO) in do_pci_enable_device()
1958 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
1973 * pci_reenable_device - Resume abandoned device
1976 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1977 * to be called by normal code, write proper resume handler and use it instead.
1979 int pci_reenable_device(struct pci_dev *dev) in pci_reenable_device()
1982 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
1990 int retval; in pci_enable_bridge()
1997 if (!dev->is_busmaster) in pci_enable_bridge()
2009 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) in pci_enable_device_flags()
2012 int err; in pci_enable_device_flags()
2013 int i, bars = 0; in pci_enable_device_flags()
2021 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2023 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2032 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2035 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2040 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2045 * pci_enable_device_io - Initialize a device for use with IO space
2048 * Initialize device before it's used by a driver. Ask low-level code
2052 int pci_enable_device_io(struct pci_dev *dev) in pci_enable_device_io()
2059 * pci_enable_device_mem - Initialize a device for use with Memory space
2062 * Initialize device before it's used by a driver. Ask low-level code
2066 int pci_enable_device_mem(struct pci_dev *dev) in pci_enable_device_mem()
2073 * pci_enable_device - Initialize device before it's used by a driver.
2076 * Initialize device before it's used by a driver. Ask low-level code
2077 * to enable I/O and memory. Wake up the device if it was suspended.
2083 int pci_enable_device(struct pci_dev *dev) in pci_enable_device()
2090 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2091 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2096 unsigned int enabled:1;
2097 unsigned int pinned:1;
2098 unsigned int orig_intx:1;
2099 unsigned int restore_intx:1;
2100 unsigned int mwi:1;
2108 int i; in pcim_release()
2111 if (this->region_mask & (1 << i)) in pcim_release()
2114 if (this->mwi) in pcim_release()
2117 if (this->restore_intx) in pcim_release()
2118 pci_intx(dev, this->orig_intx); in pcim_release()
2120 if (this->enabled && !this->pinned) in pcim_release()
2128 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2135 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2141 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2146 * pcim_enable_device - Managed pci_enable_device()
2151 int pcim_enable_device(struct pci_dev *pdev) in pcim_enable_device()
2154 int rc; in pcim_enable_device()
2158 return -ENOMEM; in pcim_enable_device()
2159 if (dr->enabled) in pcim_enable_device()
2164 pdev->is_managed = 1; in pcim_enable_device()
2165 dr->enabled = 1; in pcim_enable_device()
2172 * pcim_pin_device - Pin managed PCI device
2184 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2186 dr->pinned = 1; in pcim_pin_device()
2191 * pcibios_device_add - provide arch specific hooks when adding device dev
2198 int __weak pcibios_device_add(struct pci_dev *dev) in pcibios_device_add()
2204 * pcibios_release_device - provide arch specific hooks when releasing
2215 * pcibios_disable_device - disable arch specific PCI resources for device dev
2225 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2229 * Permits the platform to provide architecture-specific functionality when
2233 void __weak pcibios_penalize_isa_irq(int irq, int active) {} in pcibios_penalize_isa_irq()
2249 * pci_disable_enabled_device - Disable device without updating enable_cnt
2252 * NOTE: This function is a backend of PCI power management routines and is
2262 * pci_disable_device - Disable PCI device after use
2266 * anymore. This only involves disabling PCI bus-mastering, if active.
2277 dr->enabled = 0; in pci_disable_device()
2279 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2280 "disabling already-disabled device"); in pci_disable_device()
2282 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2287 dev->is_busmaster = 0; in pci_disable_device()
2292 * pcibios_set_pcie_reset_state - set reset state for device dev
2299 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, in pcibios_set_pcie_reset_state()
2302 return -EINVAL; in pcibios_set_pcie_reset_state()
2306 * pci_set_pcie_reset_state - set reset state for device dev
2312 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) in pci_set_pcie_reset_state()
2329 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2338 * pci_check_pme_status - Check if given device has generated PME.
2341 * Check the PME status of the device and if set, clear it and clear PME enable
2342 * (if set). Return 'true' if PME status and PME enable were both set or
2347 int pmcsr_pos; in pci_check_pme_status()
2351 if (!dev->pm_cap) in pci_check_pme_status()
2354 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2373 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2377 * Check if @dev has generated PME and queue a resume request for it in that
2380 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) in pci_pme_wakeup()
2382 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2383 dev->pme_poll = false; in pci_pme_wakeup()
2387 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2393 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2404 * pci_pme_capable - check the capability of PCI device to generate PME#
2410 if (!dev->pm_cap) in pci_pme_capable()
2413 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2423 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2425 if (pdev->pme_poll) { in pci_pme_list_scan()
2426 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2427 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2428 int pm_status; in pci_pme_list_scan()
2435 if (bridge && bridge->current_state != PCI_D0) in pci_pme_list_scan()
2446 if (pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2452 list_del(&pme_dev->list); in pci_pme_list_scan()
2466 if (!dev->pme_support) in __pci_pme_active()
2469 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2470 /* Clear PME_Status by writing 1 to it and enable PME# */ in __pci_pme_active()
2475 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2479 * pci_pme_restore - Restore PME configuration after config space restore.
2486 if (!dev->pme_support) in pci_pme_restore()
2489 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2490 if (dev->wakeup_prepared) { in pci_pme_restore()
2497 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2501 * pci_pme_active - enable or disable PCI device's PME# function
2515 * do this, so the PME never gets delivered and the device in pci_pme_active()
2517 * periodically walk the list of suspended devices and check in pci_pme_active()
2520 * hit, and the power savings from the devices will still be a in pci_pme_active()
2523 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2532 if (dev->pme_poll) { in pci_pme_active()
2541 pme_dev->dev = dev; in pci_pme_active()
2543 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2552 if (pme_dev->dev == dev) { in pci_pme_active()
2553 list_del(&pme_dev->list); in pci_pme_active()
2567 * __pci_enable_wake - enable PCI device as wakeup event source
2573 * When such events involves platform-specific hooks, those hooks are
2581 * -EINVAL is returned if device is not supposed to wake up the system
2582 * Error code depending on the platform is returned if both the platform and
2583 * the native mechanism fail to enable the generation of wake-up events
2585 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) in __pci_enable_wake()
2587 int ret = 0; in __pci_enable_wake()
2590 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2593 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2594 * on a hotplug event) and they need to be covered here. in __pci_enable_wake()
2600 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2606 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2610 int error; in __pci_enable_wake()
2616 * signal PME when the hierarchy above it goes into D3cold and in __pci_enable_wake()
2627 dev->wakeup_prepared = true; in __pci_enable_wake()
2631 dev->wakeup_prepared = false; in __pci_enable_wake()
2638 * pci_enable_wake - change wakeup settings for a PCI device
2646 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) in pci_enable_wake()
2648 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2649 return -EINVAL; in pci_enable_wake()
2656 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2658 * @enable: True to enable wake-up event generation; false to disable
2661 * and this function allows them to set that up cleanly - pci_enable_wake()
2662 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2667 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2669 int pci_wake_from_d3(struct pci_dev *dev, bool enable) in pci_wake_from_d3()
2678 * pci_target_state - find an appropriate low power state for a given PCI dev
2709 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2710 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2713 if (dev->current_state == PCI_D3cold) in pci_target_state()
2715 else if (!dev->pm_cap) in pci_target_state()
2718 if (wakeup && dev->pme_support) { in pci_target_state()
2725 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2726 state--; in pci_target_state()
2730 else if (dev->pme_support & 1) in pci_target_state()
2738 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2743 * it can wake up the system and/or is power manageable by the platform
2744 * (PCI_D3hot is the default) and put the device into that state.
2746 int pci_prepare_to_sleep(struct pci_dev *dev) in pci_prepare_to_sleep()
2748 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2750 int error; in pci_prepare_to_sleep()
2753 return -EIO; in pci_prepare_to_sleep()
2767 * pci_back_from_sleep - turn PCI device on during system-wide transition
2771 * Disable device's system wake-up capability and put it into D0.
2773 int pci_back_from_sleep(struct pci_dev *dev) in pci_back_from_sleep()
2775 int ret = pci_set_power_state(dev, PCI_D0); in pci_back_from_sleep()
2786 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2789 * Prepare @dev to generate wake-up events at run time and put it into a low
2792 int pci_finish_runtime_suspend(struct pci_dev *dev) in pci_finish_runtime_suspend()
2795 int error; in pci_finish_runtime_suspend()
2797 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2799 return -EIO; in pci_finish_runtime_suspend()
2812 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2815 * Return true if the device itself is capable of generating wake-up events
2817 * PME and one of its upstream bridges can generate wake-up events.
2821 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2823 if (!dev->pme_support) in pci_dev_run_wake()
2826 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2830 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2833 while (bus->parent) { in pci_dev_run_wake()
2834 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2836 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2839 bus = bus->parent; in pci_dev_run_wake()
2843 if (bus->bridge) in pci_dev_run_wake()
2844 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2851 * pci_dev_need_resume - Check if it is necessary to resume the device.
2854 * Return 'true' if the device is not runtime-suspended or it has to be
2855 * reconfigured due to wakeup settings difference between system and runtime
2857 * (system-wide) transition.
2861 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2874 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2876 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2880 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2883 * If the device is suspended and it is not configured for system wakeup,
2886 * Note that if the device's power state is D3cold and the platform check in
2892 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2894 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2897 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2900 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2904 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2907 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2913 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2918 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2920 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2923 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2927 * pci_choose_state - Choose the power state of a PCI device.
2931 * Returns PCI power state suitable for @dev and @state.
2944 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2945 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2951 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2960 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2966 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2967 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2983 .ident = "X299 DESIGNARE EX-CF",
2986 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2992 * into D3cold and back into D0 on Elo Continental Z2 board
3006 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3010 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
3026 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3028 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3035 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3047 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3065 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) in pci_dev_check_d3cold()
3070 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3072 /* ... and if it is wakeup capable to do so from D3cold. */ in pci_dev_check_d3cold()
3073 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3085 * pci_bridge_d3_update - Update bridge D3 capabilities
3094 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3106 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3110 * If D3 is currently allowed for the bridge and a child is added or in pci_bridge_d3_update()
3126 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3127 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3130 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3131 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3138 * pci_d3cold_enable - Enable D3cold for device
3147 if (dev->no_d3cold) { in pci_d3cold_enable()
3148 dev->no_d3cold = false; in pci_d3cold_enable()
3155 * pci_d3cold_disable - Disable D3cold for device
3164 if (!dev->no_d3cold) { in pci_d3cold_disable()
3165 dev->no_d3cold = true; in pci_d3cold_disable()
3172 * pci_pm_init - Initialize PM functions of given PCI device
3177 int pm; in pci_pm_init()
3181 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3182 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3183 pm_runtime_enable(&dev->dev); in pci_pm_init()
3184 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3185 dev->wakeup_prepared = false; in pci_pm_init()
3187 dev->pm_cap = 0; in pci_pm_init()
3188 dev->pme_support = 0; in pci_pm_init()
3203 dev->pm_cap = pm; in pci_pm_init()
3204 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3205 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3206 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3207 dev->d3cold_allowed = true; in pci_pm_init()
3209 dev->d1_support = false; in pci_pm_init()
3210 dev->d2_support = false; in pci_pm_init()
3213 dev->d1_support = true; in pci_pm_init()
3215 dev->d2_support = true; in pci_pm_init()
3217 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3219 dev->d1_support ? " D1" : "", in pci_pm_init()
3220 dev->d2_support ? " D2" : ""); in pci_pm_init()
3231 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
3232 dev->pme_poll = true; in pci_pm_init()
3234 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3237 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3244 dev->imm_ready = 1; in pci_pm_init()
3274 return &dev->resource[bei]; in pci_ea_get_resource()
3278 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3279 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3282 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3288 static int pci_ea_read(struct pci_dev *dev, int offset) in pci_ea_read()
3291 int ent_size, ent_offset = offset; in pci_ea_read()
3340 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3349 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3359 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3381 if (ent_size != ent_offset - offset) { in pci_ea_read()
3382 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", in pci_ea_read()
3383 ent_size, ent_offset - offset); in pci_ea_read()
3387 res->name = pci_name(dev); in pci_ea_read()
3388 res->start = start; in pci_ea_read()
3389 res->end = end; in pci_ea_read()
3390 res->flags = flags; in pci_ea_read()
3400 bei - PCI_EA_BEI_VF_BAR0, res, prop); in pci_ea_read()
3412 int ea; in pci_ea_init()
3414 int offset; in pci_ea_init()
3415 int i; in pci_ea_init()
3423 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3430 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3441 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3445 * _pci_add_cap_save_buffer - allocate buffer for saving given
3452 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, in _pci_add_cap_save_buffer()
3453 bool extended, unsigned int size) in _pci_add_cap_save_buffer()
3455 int pos; in _pci_add_cap_save_buffer()
3468 return -ENOMEM; in _pci_add_cap_save_buffer()
3470 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3471 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3472 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3478 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) in pci_add_cap_save_buffer()
3483 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) in pci_add_ext_cap_save_buffer()
3489 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3494 int error; in pci_allocate_cap_save_buffers()
3503 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3518 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3523 * pci_configure_ari - enable or disable ARI forwarding
3526 * If @dev and its upstream bridge both support ARI, enable ARI in the
3534 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3537 bridge = dev->bus->self; in pci_configure_ari()
3548 bridge->ari_enabled = 1; in pci_configure_ari()
3552 bridge->ari_enabled = 0; in pci_configure_ari()
3558 int pos; in pci_acs_flags_enabled()
3561 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3568 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3578 * pci_acs_enabled - test ACS against required flags for a given device
3588 * opportunity for peer-to-peer access. We therefore return 'true'
3595 int ret; in pci_acs_enabled()
3602 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3611 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3613 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3626 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should in pci_acs_enabled()
3627 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3628 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3635 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3644 if (!pdev->multifunction) in pci_acs_enabled()
3658 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3677 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3680 parent = pdev->bus->self; in pci_acs_path_enabled()
3687 * pci_acs_init - Initialize ACS if hardware supports it
3692 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3704 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3709 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3710 * Returns -ENOENT if no ctrl register for the BAR could be found.
3712 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) in pci_rebar_find_pos()
3714 unsigned int pos, nbars, i; in pci_rebar_find_pos()
3719 return -ENOTSUPP; in pci_rebar_find_pos()
3726 int bar_idx; in pci_rebar_find_pos()
3734 return -ENOENT; in pci_rebar_find_pos()
3738 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3745 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) in pci_rebar_get_possible_sizes()
3747 int pos; in pci_rebar_get_possible_sizes()
3758 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3767 * pci_rebar_get_current_size - get the current size of a BAR
3774 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) in pci_rebar_get_current_size()
3776 int pos; in pci_rebar_get_current_size()
3788 * pci_rebar_set_size - set a new size for a BAR
3796 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) in pci_rebar_set_size()
3798 int pos; in pci_rebar_set_size()
3813 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3821 * blocking is disabled on all upstream ports, and the root port supports
3822 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3825 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) in pci_enable_atomic_ops_to_root()
3827 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3833 * in Device Control 2 is reserved in VFs and the PF value applies in pci_enable_atomic_ops_to_root()
3836 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3837 return -EINVAL; in pci_enable_atomic_ops_to_root()
3840 return -EINVAL; in pci_enable_atomic_ops_to_root()
3843 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be in pci_enable_atomic_ops_to_root()
3845 * requesters and root ports as completers. No endpoints as in pci_enable_atomic_ops_to_root()
3846 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3855 return -EINVAL; in pci_enable_atomic_ops_to_root()
3858 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3859 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3868 return -EINVAL; in pci_enable_atomic_ops_to_root()
3874 return -EINVAL; in pci_enable_atomic_ops_to_root()
3883 return -EINVAL; in pci_enable_atomic_ops_to_root()
3886 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3896 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3901 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3902 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3908 int slot; in pci_swizzle_interrupt_pin()
3910 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
3913 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
3915 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
3918 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) in pci_get_interrupt_pin()
3922 pin = dev->pin; in pci_get_interrupt_pin()
3924 return -1; in pci_get_interrupt_pin()
3926 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
3928 dev = dev->bus->self; in pci_get_interrupt_pin()
3935 * pci_common_swizzle - swizzle INTx all the way to root bridge
3939 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3946 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
3948 dev = dev->bus->self; in pci_common_swizzle()
3951 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
3956 * pci_release_region - Release a PCI bar
3961 * Releases the PCI I/O and memory resources previously reserved by a
3965 void pci_release_region(struct pci_dev *pdev, int bar) in pci_release_region()
3980 dr->region_mask &= ~(1 << bar); in pci_release_region()
3985 * __pci_request_region - Reserved PCI I/O and memory resource
4003 static int __pci_request_region(struct pci_dev *pdev, int bar, in __pci_request_region()
4004 const char *res_name, int exclusive) in __pci_request_region()
4024 dr->region_mask |= 1 << bar; in __pci_request_region()
4030 &pdev->resource[bar]); in __pci_request_region()
4031 return -EBUSY; in __pci_request_region()
4035 * pci_request_region - Reserve PCI I/O and memory resource
4048 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) in pci_request_region()
4055 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4059 * Release selected PCI I/O and memory resources previously reserved.
4062 void pci_release_selected_regions(struct pci_dev *pdev, int bars) in pci_release_selected_regions()
4064 int i; in pci_release_selected_regions()
4072 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, in __pci_request_selected_regions()
4073 const char *res_name, int excl) in __pci_request_selected_regions()
4075 int i; in __pci_request_selected_regions()
4084 while (--i >= 0) in __pci_request_selected_regions()
4088 return -EBUSY; in __pci_request_selected_regions()
4093 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4098 int pci_request_selected_regions(struct pci_dev *pdev, int bars, in pci_request_selected_regions()
4105 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, in pci_request_selected_regions_exclusive()
4114 * pci_release_regions - Release reserved PCI I/O and memory resources
4118 * Releases all PCI I/O and memory resources previously reserved by a
4125 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4130 * pci_request_regions - Reserve PCI I/O and memory resources
4142 int pci_request_regions(struct pci_dev *pdev, const char *res_name) in pci_request_regions()
4145 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4150 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4159 * and the sysfs MMIO access will not be allowed.
4164 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) in pci_request_regions_exclusive()
4167 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4175 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, in pci_register_io_range()
4178 int ret = 0; in pci_register_io_range()
4183 return -EINVAL; in pci_register_io_range()
4187 return -ENOMEM; in pci_register_io_range()
4189 range->fwnode = fwnode; in pci_register_io_range()
4190 range->size = size; in pci_register_io_range()
4191 range->hw_start = addr; in pci_register_io_range()
4192 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4199 if (ret == -EEXIST) in pci_register_io_range()
4223 return (unsigned long)-1; in pci_address_to_pio()
4230 * pci_remap_iospace - Remap the memory mapped I/O space
4234 * Remap the memory mapped I/O space described by the @res and the CPU
4236 * architectures that have memory mapped IO functions defined (and the
4240 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) in pci_remap_iospace()
4243 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4245 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4246 return -EINVAL; in pci_remap_iospace()
4248 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4249 return -EINVAL; in pci_remap_iospace()
4259 return -ENODEV; in pci_remap_iospace()
4266 * pci_unmap_iospace - Unmap the memory mapped I/O space
4270 * architectures that have memory mapped IO functions defined (and the
4276 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4291 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4299 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, in devm_pci_remap_iospace()
4303 int error; in devm_pci_remap_iospace()
4307 return -ENOMEM; in devm_pci_remap_iospace()
4322 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4352 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4357 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4360 * All operations are managed and will be undone on driver detach.
4366 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4381 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4386 if (res->name) in devm_pci_remap_cfg_resource()
4388 res->name); in devm_pci_remap_cfg_resource()
4392 return IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4394 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4396 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4399 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4402 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4403 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4424 dev->is_busmaster = enable; in __pci_set_master()
4428 * pcibios_setup - process "pci=" kernel boot arguments
4440 * pcibios_set_master - enable PCI bus-mastering for device dev
4443 * Enables PCI bus-mastering for the device. This is the default
4467 * pci_set_master - enables bus-mastering for device dev
4470 * Enables bus-mastering on the device and calls pcibios_set_master()
4481 * pci_clear_master - disables bus-mastering for device dev
4491 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4496 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4498 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4500 int pci_set_cacheline_size(struct pci_dev *dev) in pci_set_cacheline_size()
4505 return -EINVAL; in pci_set_cacheline_size()
4524 return -EINVAL; in pci_set_cacheline_size()
4529 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4532 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4534 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4536 int pci_set_mwi(struct pci_dev *dev) in pci_set_mwi()
4541 int rc; in pci_set_mwi()
4550 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4560 * pcim_set_mwi - a device-managed pci_set_mwi()
4565 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4567 int pcim_set_mwi(struct pci_dev *dev) in pcim_set_mwi()
4573 return -ENOMEM; in pcim_set_mwi()
4575 dr->mwi = 1; in pcim_set_mwi()
4581 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4584 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4587 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4589 int pci_try_set_mwi(struct pci_dev *dev) in pci_try_set_mwi()
4600 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4603 * Disables PCI Memory-Write-Invalidate transaction on the device
4620 * pci_disable_parity - disable parity checking for device
4637 * pci_intx - enables/disables PCI INTx for device dev
4643 void pci_intx(struct pci_dev *pdev, int enable) in pci_intx()
4660 if (dr && !dr->restore_intx) { in pci_intx()
4661 dr->restore_intx = 1; in pci_intx()
4662 dr->orig_intx = !enable; in pci_intx()
4670 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4678 * We do a single dword read to retrieve both command and status. in pci_check_and_set_intx_mask()
4686 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4705 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4714 * pci_check_and_mask_intx - mask INTx on pending interrupt
4717 * Check if the device dev has its INTx line asserted, mask it and return
4727 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4730 * Check if the device dev has its INTx line asserted, unmask it if not and
4731 * return true. False is returned and the mask remains active if there was
4741 * pci_wait_for_pending_transaction - wait for pending transaction
4746 int pci_wait_for_pending_transaction(struct pci_dev *dev) in pci_wait_for_pending_transaction()
4757 * pcie_flr - initiate a PCIe function level reset
4761 * checking any flags and DEVCAP
4763 int pcie_flr(struct pci_dev *dev) in pcie_flr()
4770 if (dev->imm_ready) in pcie_flr()
4785 * pcie_reset_flr - initiate a PCIe function level reset
4791 int pcie_reset_flr(struct pci_dev *dev, bool probe) in pcie_reset_flr()
4793 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4794 return -ENOTTY; in pcie_reset_flr()
4796 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4797 return -ENOTTY; in pcie_reset_flr()
4806 static int pci_af_flr(struct pci_dev *dev, bool probe) in pci_af_flr()
4808 int pos; in pci_af_flr()
4813 return -ENOTTY; in pci_af_flr()
4815 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4816 return -ENOTTY; in pci_af_flr()
4820 return -ENOTTY; in pci_af_flr()
4826 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4827 * is used, so we use the control offset rather than status and shift in pci_af_flr()
4836 if (dev->imm_ready) in pci_af_flr()
4851 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4855 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4857 * PCI_D0. If that's the case and the device is not in a low-power state
4858 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4861 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4865 static int pci_pm_reset(struct pci_dev *dev, bool probe) in pci_pm_reset()
4869 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4870 return -ENOTTY; in pci_pm_reset()
4872 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4874 return -ENOTTY; in pci_pm_reset()
4879 if (dev->current_state != PCI_D0) in pci_pm_reset()
4880 return -EINVAL; in pci_pm_reset()
4884 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4889 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4892 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4896 * pcie_wait_for_link_status - Wait for link status change
4901 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4904 static int pcie_wait_for_link_status(struct pci_dev *pdev, in pcie_wait_for_link_status()
4922 return -ETIMEDOUT; in pcie_wait_for_link_status()
4926 * pcie_retrain_link - Request a link retrain and wait for it to complete
4934 * Return 0 if successful, or -ETIMEDOUT if training has not completed
4937 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt) in pcie_retrain_link()
4939 int rc; in pcie_retrain_link()
4952 if (pdev->clear_retrain_link) { in pcie_retrain_link()
4965 * pcie_wait_for_link_delay - Wait until link is active or inactive
4973 int delay) in pcie_wait_for_link_delay()
4975 int rc; in pcie_wait_for_link_delay()
4981 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
5015 * pcie_wait_for_link - Wait until link is active or inactive
5028 * spec says 100 ms, but firmware can lower it and we allow drivers to
5033 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) in pci_bus_max_d3cold_delay()
5036 int min_delay = 100; in pci_bus_max_d3cold_delay()
5037 int max_delay = 0; in pci_bus_max_d3cold_delay()
5039 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
5040 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
5041 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5042 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
5043 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5050 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5052 * @reset_type: reset type in human-readable form
5062 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5065 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) in pci_bridge_wait_for_secondary_bus()
5068 int delay; in pci_bridge_wait_for_secondary_bus()
5080 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
5084 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
5090 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
5096 child = list_first_entry(&dev->subordinate->devices, struct pci_dev, in pci_bridge_wait_for_secondary_bus()
5101 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
5111 * For PCIe downstream and root ports that do not support speeds in pci_bridge_wait_for_secondary_bus()
5116 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
5122 * Therefore we wait for 100 ms and check for the device presence in pci_bridge_wait_for_secondary_bus()
5134 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
5139 * whether the link is active and if not bail out early with in pci_bridge_wait_for_secondary_bus()
5142 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
5143 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5147 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5150 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
5158 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5162 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
5189 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5193 * Devices on the secondary bus are left in power-on state.
5195 int pci_bridge_secondary_bus_reset(struct pci_dev *dev) in pci_bridge_secondary_bus_reset()
5203 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe) in pci_parent_bus_reset()
5207 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5208 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5209 return -ENOTTY; in pci_parent_bus_reset()
5211 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5213 return -ENOTTY; in pci_parent_bus_reset()
5218 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5221 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe) in pci_reset_hotplug_slot()
5223 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5225 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5228 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5229 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5231 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5236 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) in pci_dev_reset_slot_function()
5238 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5239 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5240 return -ENOTTY; in pci_dev_reset_slot_function()
5242 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5245 static int pci_reset_bus_function(struct pci_dev *dev, bool probe) in pci_reset_bus_function()
5247 int rc; in pci_reset_bus_function()
5250 if (rc != -ENOTTY) in pci_reset_bus_function()
5258 device_lock(&dev->dev); in pci_dev_lock()
5264 int pci_dev_trylock(struct pci_dev *dev) in pci_dev_trylock()
5266 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5269 device_unlock(&dev->dev); in pci_dev_trylock()
5279 device_unlock(&dev->dev); in pci_dev_unlock()
5286 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5289 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5290 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5293 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5294 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5297 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5298 * reset and a simple register restore doesn't reliably return in pci_dev_save_and_disable()
5299 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5306 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5308 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5309 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5317 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5322 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5323 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5326 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5327 err_handler->reset_done(dev); in pci_dev_restore()
5330 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5346 int i, m; in reset_method_show()
5349 m = pdev->reset_methods[i]; in reset_method_show()
5363 static int reset_method_lookup(const char *name) in reset_method_lookup()
5365 int m; in reset_method_lookup()
5381 int m, n; in reset_method_store()
5385 pdev->reset_methods[0] = 0; in reset_method_store()
5397 return -ENOMEM; in reset_method_store()
5417 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5427 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5430 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5431 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5438 return -EINVAL; in reset_method_store()
5448 struct attribute *a, int n) in pci_dev_reset_method_attr_is_visible()
5455 return a->mode; in pci_dev_reset_method_attr_is_visible()
5464 * __pci_reset_function_locked - reset a PCI device function while holding
5472 * The device function is presumed to be unused and the caller is holding
5477 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5483 int __pci_reset_function_locked(struct pci_dev *dev) in __pci_reset_function_locked()
5485 int i, m, rc; in __pci_reset_function_locked()
5490 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5498 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5500 return -ENOTTY; in __pci_reset_function_locked()
5505 if (rc != -ENOTTY) in __pci_reset_function_locked()
5509 return -ENOTTY; in __pci_reset_function_locked()
5514 * pci_init_reset_methods - check whether device can be safely reset
5515 * and store supported reset mechanisms.
5519 * other functions in the same device. The PCI device must be in D0-D3hot
5522 * Stores reset mechanisms supported by device in reset_methods byte array
5527 int m, i, rc; in pci_init_reset_methods()
5537 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5538 else if (rc != -ENOTTY) in pci_init_reset_methods()
5542 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5546 * pci_reset_function - quiesce and reset a PCI device function
5555 * from __pci_reset_function_locked() in that it saves and restores device state
5556 * over the reset and takes the PCI device lock.
5561 int pci_reset_function(struct pci_dev *dev) in pci_reset_function()
5563 int rc; in pci_reset_function()
5566 return -ENOTTY; in pci_reset_function()
5581 * pci_reset_function_locked - quiesce and reset a PCI device function
5590 * from __pci_reset_function_locked() in that it saves and restores device state
5597 int pci_reset_function_locked(struct pci_dev *dev) in pci_reset_function_locked()
5599 int rc; in pci_reset_function_locked()
5602 return -ENOTTY; in pci_reset_function_locked()
5615 * pci_try_reset_function - quiesce and reset a PCI device function
5618 * Same as above, except return -EAGAIN if unable to lock device.
5620 int pci_try_reset_function(struct pci_dev *dev) in pci_try_reset_function()
5622 int rc; in pci_try_reset_function()
5625 return -ENOTTY; in pci_try_reset_function()
5628 return -EAGAIN; in pci_try_reset_function()
5645 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5648 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5649 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5650 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5662 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5664 if (dev->subordinate) in pci_bus_lock()
5665 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5674 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5675 if (dev->subordinate) in pci_bus_unlock()
5676 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5682 static int pci_bus_trylock(struct pci_bus *bus) in pci_bus_trylock()
5686 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5689 if (dev->subordinate) { in pci_bus_trylock()
5690 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
5699 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5700 if (dev->subordinate) in pci_bus_trylock()
5701 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5712 if (slot->bus->self && in pci_slot_resettable()
5713 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5716 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5717 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5719 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5720 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5732 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5733 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5736 if (dev->subordinate) in pci_slot_lock()
5737 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5746 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5747 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5749 if (dev->subordinate) in pci_slot_unlock()
5750 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5756 static int pci_slot_trylock(struct pci_slot *slot) in pci_slot_trylock()
5760 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5761 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5765 if (dev->subordinate) { in pci_slot_trylock()
5766 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5776 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5777 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5779 if (dev->subordinate) in pci_slot_trylock()
5780 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5787 * Save and disable devices from the top of the tree down while holding
5794 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5796 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5797 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5810 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5812 if (dev->subordinate) in pci_bus_restore_locked()
5813 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5818 * Save and disable devices from the top of the tree down while holding
5825 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5826 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5829 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5830 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5843 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5844 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5847 if (dev->subordinate) in pci_slot_restore_locked()
5848 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5852 static int pci_slot_reset(struct pci_slot *slot, bool probe) in pci_slot_reset()
5854 int rc; in pci_slot_reset()
5857 return -ENOTTY; in pci_slot_reset()
5864 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5873 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5878 int pci_probe_reset_slot(struct pci_slot *slot) in pci_probe_reset_slot()
5885 * __pci_reset_slot - Try to reset a PCI slot
5893 * function of the slot and any subordinate buses behind the slot are reset
5894 * through this function. PCI config space of all devices in the slot and
5895 * behind the slot is saved before and restored after reset.
5897 * Same as above except return -EAGAIN if the slot cannot be locked
5899 static int __pci_reset_slot(struct pci_slot *slot) in __pci_reset_slot()
5901 int rc; in __pci_reset_slot()
5910 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5914 rc = -EAGAIN; in __pci_reset_slot()
5919 static int pci_bus_reset(struct pci_bus *bus, bool probe) in pci_bus_reset()
5921 int ret; in pci_bus_reset()
5923 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
5924 return -ENOTTY; in pci_bus_reset()
5933 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5941 * pci_bus_error_reset - reset the bridge's subordinate bus
5948 int pci_bus_error_reset(struct pci_dev *bridge) in pci_bus_error_reset()
5950 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5954 return -ENOTTY; in pci_bus_error_reset()
5957 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5960 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5964 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5972 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5976 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5981 int pci_probe_reset_bus(struct pci_bus *bus) in pci_probe_reset_bus()
5988 * __pci_reset_bus - Try to reset a PCI bus
5991 * Same as above except return -EAGAIN if the bus cannot be locked
5993 static int __pci_reset_bus(struct pci_bus *bus) in __pci_reset_bus()
5995 int rc; in __pci_reset_bus()
6004 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
6008 rc = -EAGAIN; in __pci_reset_bus()
6014 * pci_reset_bus - Try to reset a PCI bus
6017 * Same as above except return -EAGAIN if the bus cannot be locked
6019 int pci_reset_bus(struct pci_dev *pdev) in pci_reset_bus()
6021 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
6022 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
6027 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6033 int pcix_get_max_mmrbc(struct pci_dev *dev) in pcix_get_max_mmrbc()
6035 int cap; in pcix_get_max_mmrbc()
6040 return -EINVAL; in pcix_get_max_mmrbc()
6043 return -EINVAL; in pcix_get_max_mmrbc()
6050 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6056 int pcix_get_mmrbc(struct pci_dev *dev) in pcix_get_mmrbc()
6058 int cap; in pcix_get_mmrbc()
6063 return -EINVAL; in pcix_get_mmrbc()
6066 return -EINVAL; in pcix_get_mmrbc()
6073 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6076 * valid values are 512, 1024, 2048, 4096
6081 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) in pcix_set_mmrbc()
6083 int cap; in pcix_set_mmrbc()
6088 return -EINVAL; in pcix_set_mmrbc()
6090 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
6094 return -EINVAL; in pcix_set_mmrbc()
6097 return -EINVAL; in pcix_set_mmrbc()
6100 return -E2BIG; in pcix_set_mmrbc()
6103 return -EINVAL; in pcix_set_mmrbc()
6107 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
6108 return -EIO; in pcix_set_mmrbc()
6113 return -EIO; in pcix_set_mmrbc()
6120 * pcie_get_readrq - get PCI Express read request size
6125 int pcie_get_readrq(struct pci_dev *dev) in pcie_get_readrq()
6136 * pcie_set_readrq - set PCI Express maximum memory read request
6139 * valid values are 128, 256, 512, 1024, 2048, 4096
6143 int pcie_set_readrq(struct pci_dev *dev, int rq) in pcie_set_readrq()
6146 int ret; in pcie_set_readrq()
6147 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
6150 return -EINVAL; in pcie_set_readrq()
6158 int mps = pcie_get_mps(dev); in pcie_set_readrq()
6164 v = (ffs(rq) - 8) << 12; in pcie_set_readrq()
6166 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
6167 int max_mrrs = pcie_get_readrq(dev); in pcie_set_readrq()
6171 return -EINVAL; in pcie_set_readrq()
6183 * pcie_get_mps - get PCI Express maximum payload size
6188 int pcie_get_mps(struct pci_dev *dev) in pcie_get_mps()
6199 * pcie_set_mps - set PCI Express maximum payload size
6202 * valid values are 128, 256, 512, 1024, 2048, 4096
6206 int pcie_set_mps(struct pci_dev *dev, int mps) in pcie_set_mps()
6209 int ret; in pcie_set_mps()
6212 return -EINVAL; in pcie_set_mps()
6214 v = ffs(mps) - 8; in pcie_set_mps()
6215 if (v > dev->pcie_mpss) in pcie_set_mps()
6216 return -EINVAL; in pcie_set_mps()
6227 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6228 * device and its bandwidth limitation
6234 * Walk up the PCI device chain and find the point where the minimum
6235 * bandwidth is available. Return the bandwidth available there and (if
6236 * limiting_dev, speed, and width pointers are supplied) information about
6285 * pcie_get_speed_cap - query for the PCI device's link speed capability
6302 * where only 2.5 GT/s and 5.0 GT/s speeds were defined. in pcie_get_speed_cap()
6306 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6321 * pcie_get_width_cap - query for the PCI device's link width capability
6340 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6346 * and width, multiplying them, and applying encoding overhead. The result
6362 * __pcie_print_link_status - Report the PCI device's link speed and width
6367 * capable of, report the device's maximum possible bandwidth and the
6369 * the available bandwidth, even if the device isn't constrained.
6395 * pcie_print_link_status - Report the PCI device's link speed and width
6407 * pci_select_bars - Make BAR mask from the type of resource
6413 int pci_select_bars(struct pci_dev *dev, unsigned long flags) in pci_select_bars()
6415 int i, bars = 0; in pci_select_bars()
6431 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, in pci_set_vga_state_arch()
6432 unsigned int command_bits, u32 flags) in pci_set_vga_state_arch()
6441 * pci_set_vga_state - set VGA decode state on device and parents if requested
6444 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6445 * @flags: traverse ancestors and change bridges
6448 int pci_set_vga_state(struct pci_dev *dev, bool decode, in pci_set_vga_state()
6449 unsigned int command_bits, u32 flags) in pci_set_vga_state()
6454 int rc; in pci_set_vga_state()
6475 bus = dev->bus; in pci_set_vga_state()
6477 bridge = bus->self; in pci_set_vga_state()
6488 bus = bus->parent; in pci_set_vga_state()
6501 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6505 return adev->power.flags.power_resources && in pci_pr3_present()
6506 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6512 * pci_add_dma_alias - Add a DMA devfn alias for a device
6514 * @devfn_from: alias slot and function
6517 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6518 * which is used to program permissible bus-devfn source addresses for DMA
6520 * and are useful for devices generating DMA requests beyond or different
6521 * from their logical bus-devfn. Examples include device quirks where the
6522 * device simply uses the wrong devfn, as well as non-transparent bridges
6526 * prior to any potential DMA mapping and therefore prior to driver probing
6532 unsigned int nr_devfns) in pci_add_dma_alias()
6534 int devfn_to; in pci_add_dma_alias()
6536 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6537 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6539 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6540 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6541 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6546 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6559 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6560 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6561 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6562 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6575 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6581 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6583 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6586 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6591 * pci_real_dma_dev - Get PCI DMA device for PCI device
6594 * Permits the platform to provide architecture-specific functionality to
6611 * Arches that don't want to expose struct resource to userland as-is in
6612 * sysfs and /proc can implement their own pci_resource_to_user().
6614 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, in pci_resource_to_user()
6618 *start = rsrc->start; in pci_resource_to_user()
6619 *end = rsrc->end; in pci_resource_to_user()
6626 * pci_specified_resource_alignment - get resource alignment specified by user.
6636 int align_order, count; in pci_specified_resource_alignment()
6639 int ret; in pci_specified_resource_alignment()
6687 static void pci_request_resource_alignment(struct pci_dev *dev, int bar, in pci_request_resource_alignment()
6690 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6693 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6696 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6722 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and in pci_request_resource_alignment()
6723 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6729 * the "pci=resource_alignment" argument, "resize" is true and we in pci_request_resource_alignment()
6731 * devices and we use the second. in pci_request_resource_alignment()
6738 r->start = 0; in pci_request_resource_alignment()
6739 r->end = align - 1; in pci_request_resource_alignment()
6741 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6742 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6743 r->start = align; in pci_request_resource_alignment()
6744 r->end = r->start + size - 1; in pci_request_resource_alignment()
6746 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6750 * This function disables memory decoding and releases memory resources
6753 * Later on, the kernel will assign page-aligned memory resource back
6758 int i; in pci_reassigndev_resource_alignment()
6765 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6767 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6770 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6778 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6779 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6796 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6798 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6799 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6801 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6802 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6803 r->start = 0; in pci_reassigndev_resource_alignment()
6826 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6827 return -EINVAL; in resource_alignment_store()
6831 return -ENOMEM; in resource_alignment_store()
6854 static int __init pci_resource_alignment_sysfs_init(void) in pci_resource_alignment_sysfs_init()
6875 int domain_nr; in of_pci_reserve_static_domain_nr()
6890 static int of_pci_bus_find_domain_nr(struct device *parent) in of_pci_bus_find_domain_nr()
6893 int domain_nr; in of_pci_bus_find_domain_nr()
6907 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6925 if (bus->domain_nr < 0) in of_pci_bus_release_domain_nr()
6929 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr) in of_pci_bus_release_domain_nr()
6930 ida_free(&pci_domain_nr_static_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
6932 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
6935 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) in pci_bus_find_domain_nr()
6950 * pci_ext_cfg_avail - can we access extended PCI config space?
6956 int __weak pci_ext_cfg_avail(void) in pci_ext_cfg_avail()
6966 static int __init pci_setup(char *str) in pci_setup()
7035 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
7039 * service available during an early_param() call. So we allocate memory and
7040 * copy the variable here before the init section is freed.
7043 static int __init pci_realloc_setup_params(void) in pci_realloc_setup_params()