1 // SPDX-License-Identifier: GPL-2.0
3  * Microchip Polarfire FPGA programming over slave SPI interface.
8 #include <linux/fpga/fpga-mgr.h>
12 #include <linux/spi/spi.h>
44 	struct spi_device *spi;  member
55 	 * two identical SPI transfers and use result of the later one.  in mpf_read_status()
59 			.tx_buf = &priv->tx,  in mpf_read_status()
60 			.rx_buf = &priv->rx,  in mpf_read_status()
64 			.tx_buf = &priv->tx,  in mpf_read_status()
65 			.rx_buf = &priv->rx,  in mpf_read_status()
72 	priv->tx = MPF_SPI_READ_STATUS;  in mpf_read_status()
74 	ret = spi_sync_transfer(priv->spi, xfers, 2);  in mpf_read_status()
78 	status = priv->rx;  in mpf_read_status()
82 		return -EIO;  in mpf_read_status()
87 static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)  in mpf_ops_state()  argument
89 	struct mpf_priv *priv = mgr->priv;  in mpf_ops_state()
93 	program_mode = priv->program_mode;  in mpf_ops_state()
102 static int mpf_ops_parse_header(struct fpga_manager *mgr,  in mpf_ops_parse_header()  argument
114 		dev_err(&mgr->dev, "Image buffer is not provided\n");  in mpf_ops_parse_header()
115 		return -EINVAL;  in mpf_ops_parse_header()
120 		info->header_size = header_size;  in mpf_ops_parse_header()
121 		return -EAGAIN;  in mpf_ops_parse_header()
125 	 * Go through look-up table to find out where actual bitstream starts  in mpf_ops_parse_header()
128 	blocks_num = *(buf + header_size - 1);  in mpf_ops_parse_header()
134 		info->header_size = header_size;  in mpf_ops_parse_header()
135 		return -EAGAIN;  in mpf_ops_parse_header()
141 	while (blocks_num--) {  in mpf_ops_parse_header()
148 			info->header_size = block_start;  in mpf_ops_parse_header()
150 				return -EAGAIN;  in mpf_ops_parse_header()
168 		dev_err(&mgr->dev, "Failed to parse header look-up table\n");  in mpf_ops_parse_header()
169 		return -EFAULT;  in mpf_ops_parse_header()
174 	 * Sizes of components of the bitstream are 22-bits long placed next  in mpf_ops_parse_header()
190 		component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);  in mpf_ops_parse_header()
192 		info->data_size += component_size * MPF_SPI_FRAME_SIZE;  in mpf_ops_parse_header()
205 	 *  - timeout is reached  in mpf_poll_status()
206 	 *  - mpf_read_status() returns an error  in mpf_poll_status()
207 	 *  - busy bit is cleared AND mask bits are set  in mpf_poll_status()
226 	return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0);  in mpf_spi_write()
244 	return spi_write_then_read(priv->spi, read_command, sizeof(read_command),  in mpf_spi_write_then_read()
248 static int mpf_ops_write_init(struct fpga_manager *mgr,  in mpf_ops_write_init()  argument
254 	struct mpf_priv *priv = mgr->priv;  in mpf_ops_write_init()
255 	struct device *dev = &mgr->dev;  in mpf_ops_write_init()
259 	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {  in mpf_ops_write_init()
261 		return -EOPNOTSUPP;  in mpf_ops_write_init()
269 		return -EFAULT;  in mpf_ops_write_init()
278 	priv->program_mode = true;  in mpf_ops_write_init()
287 			.tx_buf = &priv->tx,  in mpf_spi_frame_write()
300 	priv->tx = MPF_SPI_FRAME;  in mpf_spi_frame_write()
302 	return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));  in mpf_spi_frame_write()
305 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)  in mpf_ops_write()  argument
307 	struct mpf_priv *priv = mgr->priv;  in mpf_ops_write()
308 	struct device *dev = &mgr->dev;  in mpf_ops_write()
314 		return -EINVAL;  in mpf_ops_write()
329 static int mpf_ops_write_complete(struct fpga_manager *mgr,  in mpf_ops_write_complete()  argument
334 	struct mpf_priv *priv = mgr->priv;  in mpf_ops_write_complete()
335 	struct device *dev = &mgr->dev;  in mpf_ops_write_complete()
352 	priv->program_mode = false;  in mpf_ops_write_complete()
367 static int mpf_probe(struct spi_device *spi)  in mpf_probe()  argument
369 	struct device *dev = &spi->dev;  in mpf_probe()
370 	struct fpga_manager *mgr;  in mpf_probe()  local
375 		return -ENOMEM;  in mpf_probe()
377 	priv->spi = spi;  in mpf_probe()
379 	mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",  in mpf_probe()
382 	return PTR_ERR_OR_ZERO(mgr);  in mpf_probe()
386 	{ .name = "mpf-spi-fpga-mgr", },
389 MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
393 	{ .compatible = "microchip,mpf-spi-fpga-mgr" },
410 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");