kvm/x86/pmu_counters_test.c

1 // SPDX-License-Identifier: GPL-2.0
58  * compiler often thinks the feature definitions aren't compile-time constants.
137 	 * bizarre with an architecturally valid, but unsupported, version.  in guest_get_pmu_version()
144  * one "hit, assert that its count is non-zero.  If an event isn't supported or
178 			       "Expected top-down slots >= %u, got count = %lu",  in guest_assert_event_count()
337  * Limit testing to MSRs that are actually defined by Intel (in the SDM).  MSRs
338  * that aren't defined counter MSRs *probably* don't exist, but there's no
383 		 * TODO: Test a value that validates full-width writes and the  in guest_rd_wr_counters()
428 		 * KVM doesn't support non-architectural PMUs, i.e. it should  in guest_rd_wr_counters()
434 		guest_test_rdpmc(rdpmc_idx, false, -1ull);  in guest_rd_wr_counters()
451 	 * For v2+ PMUs, PERF_GLOBAL_CTRL's architectural post-RESET value is  in guest_test_gp_counters()
452 	 * "Sets bits n-1:0 and clears the upper bits", where 'n' is the number  in guest_test_gp_counters()
462 			GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0));  in guest_test_gp_counters()
578 	 * Test up to PMU v5, which is the current maximum version defined by  in test_intel_counters()
616 			 * possible non-zero, non-reserved bitmap combination  in test_intel_counters()
621 				for (k = 1; k < (BIT(NR_INTEL_ARCH_EVENTS) - 1); k++)  in test_intel_counters()
647 				for (k = 0; k <= (BIT(nr_fixed_counters) - 1); k++)  in test_intel_counters()