1 // SPDX-License-Identifier: GPL-2.0
48 		GUEST_ASSERT(count--);  in gicv3_gicd_wait_for_rwp()
53 static inline volatile void *gicr_base_cpu(uint32_t cpu)  in gicr_base_cpu()  argument
56 	return GICR_BASE_GVA + cpu * SZ_64K * 2;  in gicr_base_cpu()
59 static void gicv3_gicr_wait_for_rwp(uint32_t cpu)  in gicv3_gicr_wait_for_rwp()  argument
63 	while (readl(gicr_base_cpu(cpu) + GICR_CTLR) & GICR_CTLR_RWP) {  in gicv3_gicr_wait_for_rwp()
64 		GUEST_ASSERT(count--);  in gicv3_gicr_wait_for_rwp()
124 	 * All other fields are read-only, so no need to read CTLR first. In  in gicv3_set_eoi_split()
132 uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset)  in gicv3_reg_readl()  argument
136 	return readl(base + offset);  in gicv3_reg_readl()
139 void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val)  in gicv3_reg_writel()  argument
143 	writel(reg_val, base + offset);  in gicv3_reg_writel()
146 uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask)  in gicv3_getl_fields()  argument
148 	return gicv3_reg_readl(cpu_or_dist, offset) & mask;  in gicv3_getl_fields()
151 void gicv3_setl_fields(uint32_t cpu_or_dist, uint64_t offset,  in gicv3_setl_fields()  argument
154 	uint32_t tmp = gicv3_reg_readl(cpu_or_dist, offset) & ~mask;  in gicv3_setl_fields()
157 	gicv3_reg_writel(cpu_or_dist, offset, tmp);  in gicv3_setl_fields()
161  * We use a single offset for the distributor and redistributor maps as they
165  * map that doesn't implement it; like GICR_WAKER's offset of 0x0014 being
168 static void gicv3_access_reg(uint32_t intid, uint64_t offset,  in gicv3_access_reg()  argument
172 	uint32_t cpu = guest_get_vcpuid();  in gicv3_access_reg()  local
188 	mask = ((1U << bits_per_field) - 1) << shift;  in gicv3_access_reg()
190 	/* Set offset to the actual register holding intid's config. */  in gicv3_access_reg()
191 	offset += (intid / fields_per_reg) * (reg_bits / 8);  in gicv3_access_reg()
193 	cpu_or_dist = (intid_range == SPI_RANGE) ? DIST_BIT : cpu;  in gicv3_access_reg()
196 		gicv3_setl_fields(cpu_or_dist, offset, mask, *val << shift);  in gicv3_access_reg()
197 	*val = gicv3_getl_fields(cpu_or_dist, offset, mask) >> shift;  in gicv3_access_reg()
200 static void gicv3_write_reg(uint32_t intid, uint64_t offset,  in gicv3_write_reg()  argument
203 	gicv3_access_reg(intid, offset, reg_bits,  in gicv3_write_reg()
207 static uint32_t gicv3_read_reg(uint32_t intid, uint64_t offset,  in gicv3_read_reg()  argument
212 	gicv3_access_reg(intid, offset, reg_bits,  in gicv3_read_reg()
222 /* Sets the intid to be level-sensitive or edge-triggered. */
236 	uint32_t cpu = guest_get_vcpuid();  in gicv3_irq_enable()  local
239 	gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu);  in gicv3_irq_enable()
245 	uint32_t cpu = guest_get_vcpuid();  in gicv3_irq_disable()  local
248 	gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu);  in gicv3_irq_disable()
291 		GUEST_ASSERT(count--);  in gicv3_enable_redist()
296 static void gicv3_cpu_init(unsigned int cpu)  in gicv3_cpu_init()  argument
302 	GUEST_ASSERT(cpu < gicv3_data.nr_cpus);  in gicv3_cpu_init()
304 	redist_base_cpu = gicr_base_cpu(cpu);  in gicv3_cpu_init()
310 	 * Mark all the SGI and PPI interrupts as non-secure Group-1.  in gicv3_cpu_init()
322 	gicv3_gicr_wait_for_rwp(cpu);  in gicv3_cpu_init()
331 	/* Enable non-secure Group-1 interrupts */  in gicv3_cpu_init()
344 	 * Mark all the SPI interrupts as non-secure Group-1.  in gicv3_dist_init()
358 	/* Wait for the settings to sync-in */  in gicv3_dist_init()
379 	 * The redistributor and CPU interfaces are initialized  in gicv3_init()
416 	       ((ilog2(cfg_table_size) - 1) & GICR_PROPBASER_IDBITS_MASK));  in gic_rdist_enable_lpis()