x86/emeraldrapids/frontend.json

3         "BriefDescription": "Clears due to Unknown Branches.",
7 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
16 …to dynamically changing prefix length of the decoded instruction (by operand size prefix instructi…
29         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …-cache that holds translations of previously fetched instructions that were decoded by the legacy …
44 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
93         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
99 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
104 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
110 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
115 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
121 …structions that are delivered to the back-end after a front-end stall of at least 16 cycles. Durin…
126         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
132 …er an interval where the front-end delivered no uops for a period of at least 2 cycles which was n…
137 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
143 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
148 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
154 …t are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 c…
159 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
165 …structions that are delivered to the back-end after a front-end stall of at least 32 cycles. Durin…
170 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
176 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
181 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
187 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
192 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
198 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
203 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
209 …nstructions that are delivered to the back-end after a front-end stall of at least 8 cycles. Durin…
245 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
249 …"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction ca…
264 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
268 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
278 …"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue …
288 …": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Deco…
293 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
297 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
307 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
317 …": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Deco…
322         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
326 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
331         "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
336 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
341         "BriefDescription": "Number of switches from DSB or MITE to the MS",
347 … switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequen…
352         "BriefDescription": "Uops delivered to IDQ while MS is busy",
361 …red by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVER…
365 …to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-en…
370 …by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVER…
375 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
380 …en optimal number of uops was delivered to the back-end when the back-end is not stalled [This eve…
386 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
391 …vered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",
395 …to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-en…
400 …by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0…
405 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
410 …en optimal number of uops was delivered to the back-end when the back-end is not stalled [This eve…
416 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…