Lines Matching full:7
302 #define RT5677_R_MUTE (0x1 << 7)
303 #define RT5677_R_MUTE_SFT 7
328 #define RT5677_LOUT3_ENH_DRV (0x1 << 7)
329 #define RT5677_LOUT3_ENH_DRV_SFT (7)
336 #define RT5677_IN_DF1 (0x1 << 7)
337 #define RT5677_IN_DF1_SFT 7
403 #define RT5677_M_DAC3_L_VOL (0x1 << 7)
404 #define RT5677_M_DAC3_L_VOL_SFT 7
437 #define RT5677_M_DAC2_L_VOL (0x1 << 7)
438 #define RT5677_M_DAC2_L_VOL_SFT 7
523 #define RT5677_M_STO4_ADC_R1 (0x1 << 7)
524 #define RT5677_M_STO4_ADC_R1_SFT 7
539 #define RT5677_M_STO3_ADC_R1 (0x1 << 7)
540 #define RT5677_M_STO3_ADC_R1_SFT 7
555 #define RT5677_M_STO2_ADC_R1 (0x1 << 7)
556 #define RT5677_M_STO2_ADC_R1_SFT 7
575 #define RT5677_M_STO1_ADC_R1 (0x1 << 7)
576 #define RT5677_M_STO1_ADC_R1_SFT 7
591 #define RT5677_M_MONO_ADC_R1 (0x1 << 7)
592 #define RT5677_M_MONO_ADC_R1_SFT 7
609 #define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
610 #define RT5677_M_ADDA_MIXER1_R_SFT 7
631 #define RT5677_M_ST_DAC1_R (0x1 << 7)
632 #define RT5677_M_ST_DAC1_R_SFT 7
661 #define RT5677_M_ST_DAC2_R (0x1 << 7)
662 #define RT5677_M_ST_DAC2_R_SFT 7
693 #define RT5677_M_STO_R_DD1_R (0x1 << 7)
694 #define RT5677_M_STO_R_DD1_R_SFT 7
727 #define RT5677_M_STO_R_DD2_R (0x1 << 7)
728 #define RT5677_M_STO_R_DD2_R_SFT 7
769 #define RT5677_M_PDM2_L (0x1 << 7)
770 #define RT5677_M_PDM2_L_SFT 7
779 #define RT5677_PDM2_PW_DOWN (0x1 << 7)
948 #define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
949 #define RT5677_DMIC_4L_LH_SFT 7
950 #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
951 #define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
996 #define RT5677_PWR_DAC3 (0x1 << 7)
997 #define RT5677_PWR_DAC3_BIT 7
1026 #define RT5677_PWR_DAC_M4F_L (0x1 << 7)
1027 #define RT5677_PWR_DAC_M4F_L_BIT 7
1058 #define RT5677_PWR_FV2 (0x1 << 7)
1059 #define RT5677_PWR_FV2_BIT 7
1082 #define RT5677_PWR_CORE (0x1 << 7)
1083 #define RT5677_PWR_CORE_BIT 7
1104 #define RT5677_PWR_SR4 (0x1 << 7)
1105 #define RT5677_PWR_SR4_BIT 7
1126 #define RT5677_PWR_SR5_RDY (0x1 << 7)
1127 #define RT5677_PWR_SR5_RDY_BIT 7
1152 #define RT5677_PWR_SR6_ISO (0x1 << 7)
1153 #define RT5677_PWR_SR6_ISO_BIT 7
1184 #define RT5677_I2S_BP_MASK (0x1 << 7)
1185 #define RT5677_I2S_BP_SFT 7
1186 #define RT5677_I2S_BP_NOR (0x0 << 7)
1187 #define RT5677_I2S_BP_INV (0x1 << 7)
1226 #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
1227 #define RT5677_I2S_BCLK_MS3_SFT 7
1228 #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
1229 #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
1325 #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
1326 #define RT5677_PLL_N_SFT 7
1403 #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
1404 #define RT5677_DSP_CLK_SRC_SFT 7
1405 #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
1406 #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
1442 /* ASRC Control 7 (0x89) */
1467 #define RT5677_VAD_CLR_FLAG (1 << 7)
1468 #define RT5677_VAD_CLR_FLAG_BIT 7
1545 #define RT5677_STA_MICBIAS1_OVCD (0x1 << 7)
1546 #define RT5677_STA_MICBIAS1_OVCD_SFT 7
1625 #define RT5677_DSP_IB_01_L (0x1 << 7)
1626 #define RT5677_DSP_IB_01_L_SFT 7
1724 RT5677_AD_STEREO1_FILTER = (0x1 << 7),