Lines Matching full:7
180 #define RT5651_R_MUTE (0x1 << 7)
181 #define RT5651_R_MUTE_SFT 7
198 #define RT5651_IN_DF1 (0x1 << 7)
199 #define RT5651_IN_SFT1 7
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
212 #define RT5651_INR_SEL_SFT 7
213 #define RT5651_INR_SEL_IN4N (0x0 << 7)
214 #define RT5651_INR_SEL_MONON (0x1 << 7)
255 #define RT5651_M_MONO_ADC_R (0x1 << 7)
256 #define RT5651_M_MONO_ADC_R_SFT 7
317 #define RT5651_M_ADCMIX_R (0x1 << 7)
318 #define RT5651_M_ADCMIX_R_SFT 7
460 #define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
461 #define RT5651_IF2_ADC_SRC_SFT 7
462 #define RT5651_IF1_ADC1 (0x0 << 7)
463 #define RT5651_IF1_ADC2 (0x1 << 7)
656 #define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
657 #define RT5651_G_BST1_OM_L_SFT 7
664 #define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
665 #define RT5651_G_DAC_L1_OM_L_SFT 7
686 #define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
687 #define RT5651_G_BST1_OM_R_SFT 7
694 #define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
695 #define RT5651_G_DAC_R1_OM_R_SFT 7
762 #define RT5651_PWR_HP_L (0x1 << 7)
763 #define RT5651_PWR_HP_L_BIT 7
827 #define RT5651_PWR_IN2_L (0x1 << 7)
828 #define RT5651_PWR_IN2_L_BIT 7
847 #define RT5651_I2S_BP_MASK (0x1 << 7)
848 #define RT5651_I2S_BP_SFT 7
849 #define RT5651_I2S_BP_NOR (0x0 << 7)
850 #define RT5651_I2S_BP_INV (0x1 << 7)
1010 #define RT5651_M_TDM2_L (0x1 << 7)
1011 #define RT5651_M_TDM2_L_SFT 7
1081 #define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1082 #define RT5651_PLL_N_SFT 7
1167 /*PLL tracking mode 7 (0x8a) */
1198 #define RT5651_HP_CD_PD_MASK (0x1 << 7)
1199 #define RT5651_HP_CD_PD_SFT 7
1200 #define RT5651_HP_CD_PD_DIS (0x0 << 7)
1201 #define RT5651_HP_CD_PD_EN (0x1 << 7)
1254 #define RT5651_VLO_MASK (0x1 << 7)
1255 #define RT5651_VLO_SFT 7
1256 #define RT5651_VLO_3V (0x0 << 7)
1257 #define RT5651_VLO_32V (0x1 << 7)
1281 #define RT5651_CP_FQ_192_KHZ 7
1376 #define RT5651_EQ_CD_F (0x1 << 7)
1377 #define RT5651_EQ_CD_F_BIT 7
1398 #define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1399 #define RT5651_EQ_LPF1_M_SFT 7
1400 #define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1401 #define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1465 #define RT5651_ALC_DRC_MASK (0x1 << 7)
1466 #define RT5651_ALC_DRC_SFT 7
1467 #define RT5651_ALC_DRC_DIS (0x0 << 7)
1468 #define RT5651_ALC_DRC_EN (0x1 << 7)
1481 #define RT5651_ALC_TAR_MASK (0x1f << 7)
1482 #define RT5651_ALC_TAR_SFT 7
1520 #define RT5651_JD_SPR_MASK (0x1 << 7)
1521 #define RT5651_JD_SPR_SFT 7
1522 #define RT5651_JD_SPR_DIS (0x0 << 7)
1523 #define RT5651_JD_SPR_EN (0x1 << 7)
1547 #define RT5651_JD3_EN_STKY (0x1 << 7)
1548 #define RT5651_JD3_EN_STKY_SFT 7
1569 #define RT5651_JD1_1_INV (0x1 << 7)
1570 #define RT5651_JD1_1_INV_SFT 7
1593 #define RT5651_MB1_OC_P_MASK (0x1 << 7)
1594 #define RT5651_MB1_OC_P_SFT 7
1595 #define RT5651_MB1_OC_P_NOR (0x0 << 7)
1596 #define RT5651_MB1_OC_P_INV (0x1 << 7)
1620 #define RT5651_STA_GP2 (0x1 << 7)
1621 #define RT5651_STA_GP2_BIT 7
1646 #define RT5651_GP5_PIN_MASK (0x1 << 7)
1647 #define RT5651_GP5_PIN_SFT 7
1648 #define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1649 #define RT5651_GP5_PIN_IRQ (0x1 << 7)
1696 #define RT5651_GP3_OUT_MASK (0x1 << 7)
1697 #define RT5651_GP3_OUT_SFT 7
1698 #define RT5651_GP3_OUT_LO (0x0 << 7)
1699 #define RT5651_GP3_OUT_HI (0x1 << 7)
1734 #define RT5651_GP8_OUT_MASK (0x1 << 7)
1735 #define RT5651_GP8_OUT_SFT 7
1736 #define RT5651_GP8_OUT_LO (0x0 << 7)
1737 #define RT5651_GP8_OUT_HI (0x1 << 7)
1792 #define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1793 #define RT5651_M_BB_HPF_L_SFT 7
1810 #define RT5651_MP3_HLP_MASK (0x1 << 7)
1811 #define RT5651_MP3_HLP_SFT 7
1812 #define RT5651_MP3_HLP_DIS (0x0 << 7)
1813 #define RT5651_MP3_HLP_EN (0x1 << 7)
1852 #define RT5651_M_3D_D2R_MASK (0x1 << 7)
1853 #define RT5651_M_3D_D2R_SFT 7
1941 #define RT5651_M_ZCD_OM_L (0x1 << 7)