Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
158 /* 0x35-0x3b is reserved */
160 /* 0x3c-0x3d are same as for htype 0 */
191 /* 0x3c-0x3d are same as for htype 0 */
193 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
199 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
205 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
206 /* 0x48-0x7f reserved */
211 #define PCI_CAP_ID_PM 0x01 /* Power Management */
212 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
217 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
219 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
220 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
221 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
222 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
224 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
227 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
236 /* Power Management Registers */
243 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */
244 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
245 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
254 #define PCI_PM_CTRL 4 /* PM control and status register */
255 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
256 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
263 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
272 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
274 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
279 #define PCI_AGP_COMMAND 8 /* Control register */
283 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
295 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
307 #define PCI_MSI_FLAGS 0x02 /* Message Control */
311 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
312 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
316 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */
317 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */
318 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */
319 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */
320 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */
321 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */
323 /* MSI-X registers (in MSI-X capability) */
324 #define PCI_MSIX_FLAGS 2 /* Message Control */
327 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
337 /* MSI-X Table entry format (in memory mapped by a BAR) */
342 #define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */
348 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
354 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
355 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
383 /* 0-5 map to BARs 0-5 respectively */
389 /* 9-14 map to VF BARs 0-5 respectively */
392 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
395 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
399 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
400 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
403 /* 0x08-0xfc reserved */
412 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
415 /* PCI-X registers (Type 0 (non-bridge) devices) */
436 #define PCI_X_STATUS 4 /* PCI-X capabilities */
439 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
450 #define PCI_X_ECC_CSR 8 /* ECC control and status */
455 /* PCI-X registers (Type 1 (bridge) devices) */
461 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
477 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
480 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
481 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
482 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
483 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
484 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
498 #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */
499 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
500 #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */
501 #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */
503 #define PCI_EXP_DEVCTL 0x08 /* Device Control */
505 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
518 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
530 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
533 #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */
550 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */
554 #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
555 #define PCI_EXP_LNKCTL 0x10 /* Link Control */
556 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
560 #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
565 #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
590 #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
593 #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */
594 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
595 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
596 #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */
597 #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */
601 #define PCI_EXP_SLTCTL 0x18 /* Slot Control */
603 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
607 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
608 #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
613 #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
614 #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */
615 #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */
616 #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */
617 #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
618 #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */
619 #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
620 #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
622 #define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */
623 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
626 #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
634 #define PCI_EXP_RTCTL 0x1c /* Root Control */
636 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
649 * The Device Capabilities 2, Device Status 2, Device Control 2,
650 * Link Capabilities 2, Link Status 2, Link Control 2,
651 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
657 #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */
658 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
667 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
668 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
669 #define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefixes */
670 #define PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */
672 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
673 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
693 #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
703 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
708 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
709 #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */
712 /* Extended Capabilities (PCI-X 2.0 and Express) */
720 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
722 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
724 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
727 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
728 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
729 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
738 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
744 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
747 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
764 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
787 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
804 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
812 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
850 /* Power Budgeting */
853 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
858 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
870 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
871 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
906 #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */
910 /* Alternative Routing-ID Interpretation */
915 #define PCI_ARI_CTRL 0x06 /* ARI Control Register */
926 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
933 #define PCI_PRI_CTRL 0x04 /* PRI control register */
950 #define PCI_PASID_CTRL 0x06 /* PASID control register */
957 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
960 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
966 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
993 #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */
997 /* Access Control Service */
1004 #define PCI_ACS_EC 0x0020 /* P2P Egress Control */
1006 #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
1007 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */
1008 #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
1012 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
1020 #define PCI_REBAR_CTRL 8 /* control register */
1027 /* Dynamic Power Allocation */
1029 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1046 #define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */
1051 #define PCI_TPH_CTRL 8 /* control register */
1061 /* Downstream Port Containment */
1064 #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */
1071 #define PCI_EXP_DPC_CTL 0x06 /* DPC control */
1084 #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */
1107 #define PCI_PTM_CTRL 0x08 /* PTM Control */
1113 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1114 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1118 #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */
1119 #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */
1120 #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */
1121 #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */
1122 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1123 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1131 #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
1135 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1136 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
1140 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1148 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
1157 #define PCI_NPEM_CTRL 0x08 /* NPEM control register */
1162 * are corresponding for capability and control registers.
1191 #define PCI_DOE_CTRL 0x08 /* DOE Control Register */
1204 /* DOE Data Object - note not actually registers */