Lines Matching full:invalidation

747  * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
749  * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
750  * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3
759  *                                           stage-1 cache invalidation
760  * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
769  * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
777  * The Intel VT-d specific invalidation data for user-managed stage-1 cache
778  * invalidation in nested translation. Userspace uses this structure to
794  * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
796  * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
818  * @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation
819  * @data_uptr: User pointer to an array of driver-specific cache invalidation
822  *             type of all the entries in the invalidation request array. It
825  * @entry_num: Input the number of cache invalidation requests in the array.
834  * Each ioctl can support one or more cache invalidation requests in the array
837  * An empty invalidation request array by setting @entry_num==0 is allowed, and
974  * - Non-device-affiliated event reporting, e.g. invalidation queue errors
977  * - Delivery of paravirtualized invalidation
978  * - Direct assigned invalidation queues