1 /* SPDX-License-Identifier: GPL-2.0-or-later
38  * INTERFACES between SPI controller-side drivers and SPI target protocol handlers,
44  * struct spi_statistics - statistics for spi transfers
45  * @syncp:         seqcount to protect members in this struct for per-cpu update
46  *                 on 32-bit systems
48  * @messages:      number of spi-messages handled
97 		u64_stats_update_begin(&__lstats->syncp);		\
98 		u64_stats_add(&__lstats->field, count);			\
99 		u64_stats_update_end(&__lstats->syncp);			\
108 		u64_stats_update_begin(&__lstats->syncp);		\
109 		u64_stats_inc(&__lstats->field);			\
110 		u64_stats_update_end(&__lstats->syncp);			\
115  * struct spi_delay - SPI delay information
133  * struct spi_device - Controller side proxy for an SPI target device
139  * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
147  *	like eight or 12 bits are common.  In-memory wordsizes are
156  * @controller_data: Board-specific definitions for controller, such as
200 	 * only half-duplex, the wait state detection needs to be implemented
214 #define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
222 	struct spi_delay	word_delay; /* Inter-word delay */
241 	 *  - memory packing (12 bit samples into low bits, others zeroed)
242 	 *  - priority
243 	 *  - chipselect delays
244 	 *  - ...
257 	return (spi && get_device(&spi->dev)) ? spi : NULL;  in spi_dev_get()
263 		put_device(&spi->dev);  in spi_dev_put()
269 	return spi->controller_state;  in spi_get_ctldata()
274 	spi->controller_state = state;  in spi_set_ctldata()
281 	dev_set_drvdata(&spi->dev, data);  in spi_set_drvdata()
286 	return dev_get_drvdata(&spi->dev);  in spi_get_drvdata()
291 	return spi->chip_select[idx];  in spi_get_chipselect()
296 	spi->chip_select[idx] = chipselect;  in spi_set_chipselect()
301 	return spi->cs_gpiod[idx];  in spi_get_csgpiod()
306 	spi->cs_gpiod[idx] = csgpiod;  in spi_set_csgpiod()
321  * struct spi_driver - Host side "protocol" driver
359  * spi_unregister_driver - reverse effect of spi_register_driver
366 		driver_unregister(&sdrv->driver);  in spi_unregister_driver()
376  * module_spi_driver() - Helper macro for registering a SPI driver
388  * struct spi_controller - interface to SPI host or target controller
391  * @bus_num: board-specific (and often SOC-specific) identifier for a
410  * @devm_allocated: whether the allocation of this struct is devres-managed
429  * @cleanup: frees controller-specific state
439  * @cur_msg: the currently in-flight message
440  * @cur_msg_completion: a completion for the current in-flight message
450  * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip
482  *                  - return 0 if the transfer is finished,
483  *                  - return 1 if the transfer is still in progress. When
488  *                    spi_transfer->error first, before calling
499  *	offload instance. Implementations should return -ENODEV if no match is
520  * @dummy_rx: dummy receive buffer for full-duplex devices
521  * @dummy_tx: dummy transmit buffer for full-duplex devices
526  *	time snapshot in @spi_transfer->ptp_sts as close as possible to the
527  *	moment in time when @spi_transfer->ptp_sts_word_pre and
528  *	@spi_transfer->ptp_sts_word_post were transmitted.
530  *	close to the driver hand-over as possible.
535  * @defer_optimize_message: set to true if controller cannot pre-optimize messages
557 	 * board-specific. Usually that simplifies to being SoC-specific.
559 	 * and one board's schematics might show it using SPI-2. Software
566 	 * might use board-specific GPIOs.
583 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
584 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
600 	 * The spi-controller has multi chip select capability and can
601 	 * assert/de-assert more than one chip select at once.
605 	/* Flag indicating if the allocation of this struct is devres-managed */
646 	 * configuring CS timing.
649 	 * to configure specific CS timing through spi_set_cs_timing() after
657 	 * + The transfer() method may not sleep; its main role is
659 	 * + For now there's no remove-from-queue operation, or
742 	/* Optimized handlers for SPI memory-like operations. */
786 	return dev_get_drvdata(&ctlr->dev);  in spi_controller_get_devdata()
792 	dev_set_drvdata(&ctlr->dev, data);  in spi_controller_set_devdata()
797 	if (!ctlr || !get_device(&ctlr->dev))  in spi_controller_get()
805 		put_device(&ctlr->dev);  in spi_controller_put()
810 	return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;  in spi_controller_is_target()
889 	return ERR_PTR(-ENODEV);  in acpi_spi_device_alloc()
907  * struct spi_res - SPI resource management structure
910  * @data:    extra data allocated for the specific use-case
912  * This is based on ideas from devres, but focused on life-cycle
921 /*---------------------------------------------------------------------------*/
941  * struct spi_transfer - a read/write buffer pair
942  * @tx_buf: data to be written (DMA-safe memory), or NULL
943  * @rx_buf: data to be read (DMA-safe memory), or NULL
965  * @effective_speed_hz: the effective SCK-speed that was used to
974  *	transfers. See %SPI_OFFLOAD_XFER_* in spi-offload.h.
986  *	purposefully (instead of setting to spi_transfer->len - 1) to denote
987  *	that a transfer-level snapshot taken from within the driver may still
991  *	hardware has some sort of assist for retrieving exact transfer timing,
1014  * In-memory data values are always in native CPU byte order, translated
1015  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
1019  * When the word size of the SPI transfer is not a power-of-two multiple
1020  * of eight bits, those in-memory words include extra bits.  In-memory
1021  * words are always seen by protocol drivers as right-justified, so the
1035  * stay selected until the next transfer.  On multi-device SPI busses
1045  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
1051  * Zero-initialize every field you don't set up explicitly, to
1083 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */
1084 #define	SPI_NBITS_DUAL		0x02 /* 2-bit transfer */
1085 #define	SPI_NBITS_QUAD		0x04 /* 4-bit transfer */
1086 #define	SPI_NBITS_OCTAL	0x08 /* 8-bit transfer */
1095 	/* Use %SPI_OFFLOAD_XFER_* from spi-offload.h */
1107  * struct spi_message - one multi-segment SPI transaction
1110  * @pre_optimized: peripheral driver pre-optimized the message
1135  * Zero-initialize every field you don't set up explicitly, to
1158 	 * Some controller drivers (message-at-a-time queue processing)
1160 	 * others (with multi-message pipelines) could need a flag to
1196 	INIT_LIST_HEAD(&m->transfers);  in spi_message_init_no_memset()
1197 	INIT_LIST_HEAD(&m->resources);  in spi_message_init_no_memset()
1209 	list_add_tail(&t->transfer_list, &m->transfers);  in spi_message_add_tail()
1215 	list_del(&t->transfer_list);  in spi_transfer_del()
1221 	return spi_delay_exec(&t->delay, t);  in spi_transfer_delay_exec()
1225  * spi_message_init_with_transfers - Initialize spi_message and append transfers
1260 	spi_message_init_no_memset(&mwt->m);  in spi_message_alloc()
1262 		spi_message_add_tail(&mwt->t[i], &mwt->m);  in spi_message_alloc()
1264 	return &mwt->m;  in spi_message_alloc()
1284 	struct spi_controller *ctlr = spi->controller;  in spi_max_message_size()
1286 	if (!ctlr->max_message_size)  in spi_max_message_size()
1288 	return ctlr->max_message_size(spi);  in spi_max_message_size()
1294 	struct spi_controller *ctlr = spi->controller;  in spi_max_transfer_size()
1298 	if (ctlr->max_transfer_size)  in spi_max_transfer_size()
1299 		tr_max = ctlr->max_transfer_size(spi);  in spi_max_transfer_size()
1306  * spi_is_bpw_supported - Check if bits per word is supported
1317 	u32 bpw_mask = spi->controller->bits_per_word_mask;  in spi_is_bpw_supported()
1326  * spi_controller_xfer_timeout - Compute a suitable timeout value
1339 	return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U);  in spi_controller_xfer_timeout()
1342 /*---------------------------------------------------------------------------*/
1351  * struct spi_replaced_transfers - structure describing the spi_transfer
1360  *                      are to get re-inserted
1362  * @inserted_transfers: array of spi_transfers of array-size @inserted,
1378 /*---------------------------------------------------------------------------*/
1389 /*---------------------------------------------------------------------------*/
1403  * spi_sync_transfer - synchronous SPI data transfer
1427  * spi_write - SPI synchronous write
1450  * spi_read - SPI synchronous read
1478  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1500  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1505  * The number is returned in wire-order, which is at least sometimes
1506  * big-endian.
1525  * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1531  * convert the read 16 bit data word from big-endian to native endianness.
1551 /*---------------------------------------------------------------------------*/
1563  * support for non-static configurations too; enough to handle adding
1564  * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1568  * struct spi_board_info - board-specific template for a SPI device
1571  *	data stored there is driver-specific.
1577  *	from the chip datasheet and board-specific signal quality issues.
1591  * These structures are used in two places.  Their primary role is to
1592  * be stored in tables of board-specific device descriptors, which are
1595  * initializes.  A secondary (and atypical) role is as a parameter to
1638 	 *  - quirks like clock rate mattering when not selected
1684 	return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);  in spi_transfer_is_last()