include/linux/pxa2xx_ssp.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
57 #define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */
72 #define SSCR1_LBM	BIT(2)		/* Loop-Back Mode */
85 #define RX_THRESH_DFLT	8
86 #define TX_THRESH_DFLT	8
88 #define SSSR_TFL_MASK	GENMASK(11, 8)	/* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK	GENMASK(15, 12)	/* Receive FIFO Level mask */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..16] */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..16] */
99 #define CE4100_SSSR_TFL_MASK	GENMASK(9, 8)	/* Transmit FIFO Level mask */
100 #define CE4100_SSSR_RFL_MASK	GENMASK(13, 12)	/* Receive FIFO Level mask */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..4] */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */
112 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */
119 #define QUARK_X1000_SSSR_TFL_MASK	GENMASK(12, 8)	/* Transmit FIFO Level mask */
120 #define QUARK_X1000_SSSR_RFL_MASK	GENMASK(17, 13)	/* Receive FIFO Level mask */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..32] */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)	/* level [1..32] */
131 #define SSCR0_PSP		(3 << 4)	/* PSP - Programmable Serial Protocol */
137 #define SSCR1_TINTE		BIT(19)		/* Receiver Time-out Interrupt enable */
152 #define SSSR_TINT		BIT(19)		/* Receiver Time-out Interrupt */
187 #define SFIFOL			0x68		/* FIFO level */
193 #define SFIFOL_TFL_MASK		GENMASK(15, 0)	/* Transmit FIFO Level mask */
194 #define SFIFOL_RFL_MASK		GENMASK(31, 16)	/* Receive FIFO Level mask */
197 #define SFIFOTT_TxThresh(x)	(((x) - 1) << 0)	/* TX FIFO trigger threshold / level */
199 #define SFIFOTT_RxThresh(x)	(((x) - 1) << 16)	/* RX FIFO trigger threshold / level */
202 #define SSITF			0x44		/* TX FIFO trigger level */
203 #define SSITF_TxHiThresh(x)	(((x) - 1) << 0)
204 #define SSITF_TxLoThresh(x)	(((x) - 1) << 8)
206 #define SSIRF			0x48		/* RX FIFO trigger level */
207 #define SSIRF_RxThresh(x)	((x) - 1)
253  * pxa_ssp_write_reg - Write to a SSP register
261 	__raw_writel(val, dev->mmio_base + reg);  in pxa_ssp_write_reg()
265  * pxa_ssp_read_reg - Read from a SSP register
272 	return __raw_readl(dev->mmio_base + reg);  in pxa_ssp_read_reg()