Lines Matching defs:pci_dev
332 struct pci_dev { struct
355 struct pci_dev *rcec; /* Associated RCEC device */ argument
357 u32 devcap; /* PCIe Device Capabilities */
358 u16 rebar_cap; /* Resizable BAR capability offset */
359 u8 pcie_cap; /* PCIe capability offset */
360 u8 msi_cap; /* MSI capability offset */
361 u8 msix_cap; /* MSI-X capability offset */
362 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
363 u8 rom_base_reg; /* Config register controlling ROM */
364 u8 pin; /* Interrupt pin this device uses */
365 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
366 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
368 struct pci_driver *driver; /* Driver bound to this device */
369 u64 dma_mask; /* Mask of the bits of bus address this
375 struct device_dma_parameters dma_parms;
377 pci_power_t current_state; /* Current operating state. In ACPI,
380 u8 pm_cap; /* PM capability offset */
381 unsigned int pme_support:5; /* Bitmask of states from which PME#
383 unsigned int pme_poll:1; /* Poll device's PME status bit */
384 unsigned int pinned:1; /* Whether this dev is pinned */
385 unsigned int config_rrs_sv:1; /* Config RRS software visibility */
386 unsigned int imm_ready:1; /* Supports Immediate Readiness */
387 unsigned int d1_support:1; /* Low power state D1 is supported */
388 unsigned int d2_support:1; /* Low power state D2 is supported */
389 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
390 unsigned int no_d3cold:1; /* D3cold is forbidden */
391 unsigned int bridge_d3:1; /* Allow D3 for bridge */
392 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
393 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
395 unsigned int wakeup_prepared:1;
396 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
397 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
398 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
401 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
403 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
404 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
406 u16 l1ss; /* L1SS Capability pointer */
408 struct pcie_link_state *link_state; /* ASPM link state */
409 unsigned int ltr_path:1; /* Latency Tolerance Reporting
412 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
413 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */
415 pci_channel_state_t error_state; /* Current connectivity state */
416 struct device dev; /* Generic device interface */
418 int cfg_size; /* Size of config space */
424 unsigned int irq;
425 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
426 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
428 bool match_driver; /* Skip attaching driver */
430 unsigned int transparent:1; /* Subtractive decode bridge */
431 unsigned int io_window:1; /* Bridge has I/O window */
432 unsigned int pref_window:1; /* Bridge has pref mem window */
433 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
434 unsigned int multifunction:1; /* Multi-function device */
436 unsigned int is_busmaster:1; /* Is busmaster */
437 unsigned int no_msi:1; /* May not use MSI */
438 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
439 unsigned int block_cfg_access:1; /* Config space access blocked */
440 unsigned int broken_parity_status:1; /* Generates false positive parity */
441 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
442 unsigned int msi_enabled:1;
443 unsigned int msix_enabled:1;
444 unsigned int ari_enabled:1; /* ARI forwarding */
445 unsigned int ats_enabled:1; /* Address Translation Svc */
446 unsigned int pasid_enabled:1; /* Process Address Space ID */
447 unsigned int pri_enabled:1; /* Page Request Interface */
448 unsigned int tph_enabled:1; /* TLP Processing Hints */
449 unsigned int is_managed:1; /* Managed via devres */
450 unsigned int is_msi_managed:1; /* MSI release via devres installed */
451 unsigned int needs_freset:1; /* Requires fundamental reset */
452 unsigned int state_saved:1;
453 unsigned int is_physfn:1;
454 unsigned int is_virtfn:1;
455 unsigned int is_hotplug_bridge:1;
456 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
457 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
483 pci_dev_flags_t dev_flags; argument
484 atomic_t enable_cnt; /* pci_enable_device has been called */
486 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
487 u32 saved_config_space[16]; /* Config space saved at suspend time */
488 struct hlist_head saved_cap_space;
489 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
490 …uct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
515 struct pci_dev *physfn; /* VF: related PF */ argument
517 u16 ats_cap; /* ATS Capability offset */
518 u8 ats_stu; /* ATS Smallest Translation Unit */
521 u16 pri_cap; /* PRI Capability offset */
522 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
523 unsigned int pasid_required:1; /* PRG Response PASID Required */
526 u16 pasid_cap; /* PASID Capability offset */
527 u16 pasid_features;
530 struct pci_p2pdma __rcu *p2pdma;
533 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
536 struct npem *npem; /* Native PCIe Enclosure Management */
560 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) in pci_physfn() argument
763 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) in pci_dev_msi_enabled()
768 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } in pci_dev_msi_enabled()