linux/mtd/rawnand.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8  *	Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50  * Standard NAND flash commands
75 #define NAND_CMD_NONE		-1
84 #define NAND_DATA_IFACE_CHECK_ONLY	-1
93 /* Enable Hardware ECC before syndrome is read back from flash */
97  * Enable generic NAND 'page erased' check. This check is only done when
98  * ecc.correct() returns -EBADMSG.
109 /* Buswidth is 16 bit */
124  * Chip requires ready check on read (for auto-incremented sequential read).
133 /* Device is one of 'new' xD cards that expose fake nand command set */
136 /* Device behaves just like nand, but is readonly */
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
160  * Autodetect nand buswidth with readid/onfi.
174  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175  * on the default ->cmdfunc() implementation, you may want to let the core
176  * handle the tCCS delay which is required when a column change (RNDIN or
177  * RNDOUT) is requested.
184  * Whether the NAND chip is a boot medium. Drivers might use this information
185  * to select ECC algorithms supported by the boot ROM or similar restrictions.
190  * Do not try to tweak the timings at runtime. This is needed when the
225  * struct nand_parameters - NAND generic parameters from the parameter page
227  * @supports_set_get_features: The NAND chip supports setting/getting features
228  * @supports_read_cache: The NAND chip supports read cache operations
245 /* The maximum expected count of bytes in the NAND ID sequence */
249  * struct nand_id - NAND id structure
259  * struct nand_ecc_step_info - ECC step information of ECC engine
271  * struct nand_ecc_caps - capability of ECC engine
297  * struct nand_ecc_ctrl - Control structure for ECC
309  * @calc_buf:	buffer for calculated ECC, size is oobsize.
310  * @code_buf:	buffer for ECC read from flash, size is oobsize.
312  *		be provided if an hardware ECC is available
316  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
317  *		ECC strength, or any other error code if the error is not
319  *		If -EBADMSG is returned the input buffers should be left
323  *			controller and always return contiguous in-band and
324  *			out-of-band data even if they're not stored
325  *			contiguously on the NAND chip (e.g.
326  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
327  *			out-of-band data).
331  *			in-band and out-of-band data. ECC controller is
334  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
335  *			out-of-band data).
338  *		any single ECC step, -EIO hw error
388  * struct nand_sdr_timings - SDR NAND chip timings
390  * This struct defines the timing requirements of a SDR NAND chip.
391  * These information can be found in every NAND datasheets and the timings
393  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf
409  * @tCHZ_max: CE# high to output hi-Z
418  * @tIR_min: Output hi-Z to RE# low
425  * @tRHZ_max: RE# high to output hi-Z
480  * struct nand_nvddr_timings - NV-DDR NAND chip timings
482  * This struct defines the timing requirements of a NV-DDR NAND data interface.
483  * These information can be found in every NAND datasheets and the timings
485  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
486  * (chapter 4.18.2 NV-DDR)
511  * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
512  * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
567  * between SDR and NV-DDR, timings related to the internal chip behavior are
569  * the same definition and are shared in both SDR and NV-DDR timing structures:
570  * - tADL_min
571  * - tBERS_max
572  * - tCCS_min
573  * - tFEAT_max
574  * - tPROG_max
575  * - tR_max
576  * - tRR_min
577  * - tRST_max
578  * - tWB_max
584 		nand_get_sdr_timings(conf)->timing_name :	\
585 		nand_get_nvddr_timings(conf)->timing_name
594  * enum nand_interface_type - NAND interface type
604  * struct nand_interface_config - NAND interface timing
608  * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
609  * @timings.nvddr: Use it when @type is %NAND_NVDDR_IFACE.
623  * nand_interface_is_sdr - get the interface type
628 	return conf->type == NAND_SDR_IFACE;  in nand_interface_is_sdr()
632  * nand_interface_is_nvddr - get the interface type
637 	return conf->type == NAND_NVDDR_IFACE;  in nand_interface_is_nvddr()
641  * nand_get_sdr_timings - get SDR timing from data interface
648 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
650 	return &conf->timings.sdr;  in nand_get_sdr_timings()
654  * nand_get_nvddr_timings - get NV-DDR timing from data interface
661 		return ERR_PTR(-EINVAL);  in nand_get_nvddr_timings()
663 	return &conf->timings.nvddr;  in nand_get_nvddr_timings()
667  * struct nand_op_cmd_instr - Definition of a command instruction
675  * struct nand_op_addr_instr - Definition of an address instruction
685  * struct nand_op_data_instr - Definition of a data instruction
688  * @buf.in: buffer to fill when reading from the NAND chip
689  * @buf.out: buffer to read from when writing to the NAND chip
690  * @force_8bit: force 8-bit access
693  * and are from the controller perspective, so a "in" is a read from the NAND
694  * chip while a "out" is a write to the NAND chip.
706  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
714  * enum nand_op_instr_type - Definition of all instruction types
730  * struct nand_op_instr - Instruction object
734  * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
735  * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
736  * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
738  * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
757  * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
762  * Cast to type of dividend is needed here to guarantee that the result won't
763  * be an unsigned long long when the dividend is an unsigned long (or smaller),
764  * which is what the compiler does when it sees ternary operator with 2
845  * struct nand_subop - a sub operation
846  * @cs: the CS line to select for this NAND sub-operation
850  *			   of the sub-operation
852  *			of the sub-operation
857  * When an operation cannot be handled as is by the NAND controller, it will
858  * be split by the parser into sub-operations which will be passed to the
879  * struct nand_op_parser_addr_constraints - Constraints for address instructions
888  * struct nand_op_parser_data_constraints - Constraints for data instructions
896  * struct nand_op_parser_pattern_elem - One element of a pattern
898  * @optional: whether this element of the pattern is optional or mandatory
946  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
949  * @exec: the function that will issue a sub-operation
951  * A pattern is a list of elements, each element reprensenting one instruction
952  * with its constraints. The pattern itself is used by the core to match NAND
953  * chip operation with NAND controller operations.
954  * Once a match between a NAND controller operation pattern and a NAND chip
955  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
956  * hook is called so that the controller driver can issue the operation on the
978  * struct nand_op_parser - NAND controller operation parser descriptor
982  * The parser descriptor is just an array of supported patterns which will be
984  * NAND operation (or tries to determine if a specific operation is supported).
986  * It is worth mentioning that patterns will be tested in their declaration
989  * the list. Usually, this is where you put single instruction patterns.
1004  * struct nand_operation - NAND operation descriptor
1005  * @cs: the CS line to select for this NAND operation
1007  *		 de-asserted (ERASE, PROG, ...)
1011  * The actual operation structure that will be passed to chip->exec_op().
1043 	switch (instr->type) {  in nand_op_trace()
1046 			 instr->ctx.cmd.opcode);  in nand_op_trace()
1050 			 instr->ctx.addr.naddrs,  in nand_op_trace()
1051 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
1052 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
1053 			 instr->ctx.addr.addrs);  in nand_op_trace()
1057 			 instr->ctx.data.len,  in nand_op_trace()
1058 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1059 			 ", force 8-bit" : "");  in nand_op_trace()
1063 			 instr->ctx.data.len,  in nand_op_trace()
1064 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1065 			 ", force 8-bit" : "");  in nand_op_trace()
1069 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
1076  * struct nand_controller_ops - Controller operations
1078  * @attach_chip: this method is called after the NAND detection phase after
1081  *		 provided by the NAND chip or device tree. Typically used to
1084  *		 This hook is optional.
1086  *		 nand_controller_ops->attach_chip().
1087  *		 This hook is optional.
1088  * @exec_op:	 controller specific method to execute NAND operations.
1089  *		 This method replaces chip->legacy.cmdfunc(),
1090  *		 chip->legacy.{read,write}_{buf,byte,word}(),
1091  *		 chip->legacy.dev_ready() and chip->legacy.waitfunc().
1092  * @setup_interface: setup the data interface and timing. If chipnr is set to
1095  *		     This hook is optional.
1108  * struct nand_controller - Structure used to describe a NAND controller
1110  * @lock:		lock used to serialize accesses to the NAND controller
1111  * @ops:		NAND controller operations.
1112  * @supported_op:	NAND controller known-to-be-supported operations,
1118  * @controller_wp:	the controller is in charge of handling the WP pin.
1132 	mutex_init(&nfc->lock);  in nand_controller_init()
1136  * struct nand_legacy - NAND chip legacy fields/hooks
1148  *	       If set to NULL no access to ready/busy is available and the
1149  *	       ready/busy information is read from the chip status register.
1151  * @block_bad: check if a block is bad, using OOB markers
1153  * @set_features: set the NAND chip features
1154  * @get_features: get the NAND chip features
1187  * struct nand_chip_ops - NAND chip operations
1192  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1206  * struct nand_manufacturer - NAND manufacturer structure
1216  * struct nand_secure_region - NAND secure region structure
1226  * struct nand_chip - NAND Private Flash Chip Data
1227  * @base: Inherit from the generic NAND device
1228  * @id: Holds NAND ID
1231  * @ops: NAND chip operations
1234  *          existing driver that is using those fields/hooks, you should
1239  * @current_interface_config: The currently used NAND interface configuration
1240  * @best_interface_config: The best NAND interface configuration which fits both
1241  *                         the NAND chip and NAND controller constraints. If
1250  *                position; i.e., BBM = 11110111b is good when badblockbits = 7
1258  * @pagemask: Page number mask = number of (pages / chip) - 1
1260  * @data_buf: Buffer for data, size is (page size + oobsize)
1264  * @pagecache.page: Page number currently in the cache. -1 means no page is
1268  *        to the NAND device
1269  * @suspended: Set to 1 when the device is suspended, 0 when it's not
1270  * @resume_wq: wait queue to sleep if rawnand is in suspended state.
1271  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1273  *          NAND Controller drivers should not modify this value, but they're
1279  * @cont_read.ongoing: Whether a continuous read is ongoing or not
1283  * @controller: The hardware controller	structure which is shared among multiple
1355 	return &chip->base.mtd;  in nand_to_mtd()
1360 	return chip->priv;  in nand_get_controller_data()
1365 	chip->priv = priv;  in nand_set_controller_data()
1371 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1376 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1391  * nand_get_interface_config - Retrieve the current interface configuration
1392  *                             of a NAND chip
1393  * @chip: The NAND chip
1398 	return chip->current_interface_config;  in nand_get_interface_config()
1402  * A helper for defining older NAND chips where the second ID byte fully
1404  * size). All these chips have 512 bytes NAND page size.
1414  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1426 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1427 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1430  * struct nand_flash_dev - NAND Flash Device ID Structure
1431  * @name: a human-readable name of the NAND chip
1438  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1439  *            well as the eraseblock size) is determined from the extended NAND
1478  * Check if it is a SLC nand.
1479  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1484 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1485 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1486 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1490  * nand_opcode_8bits - Check if the opcode's address should be sent only on the
1552 /* Reset and initialize a NAND device */
1555 /* NAND operation helpers */
1586 /* Scan and identify a NAND device */
1599  * Free resources held by the NAND device, must be called on error after a
1612 /* Select/deselect a NAND target. */
1621  * nand_get_data_buf() - Get the internal page buffer
1622  * @chip: NAND chip object
1624  * Returns the pre-allocated page buffer after invalidating the cache. This
1636 	chip->pagecache.page = -1;  in nand_get_data_buf()
1638 	return chip->data_buf;  in nand_get_data_buf()
1641 /* Parse the gpio-cs property */