1225 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1255 	/* NUM OF CAP Types */
1287 #define MLX5_CAP_GEN(mdev, cap) \  argument
1288 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1290 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1291 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1293 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1294 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1296 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1297 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1299 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1300 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1302 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1303 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1305 #define MLX5_CAP_ETH(mdev, cap) \  argument
1307 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1309 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1311 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1313 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1314 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1316 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1317 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1319 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1320 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1322 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1323 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1325 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1326 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1328 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1329 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1331 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1332 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1334 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1335 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1337 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1338 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1340 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1341 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1343 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1344 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1346 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1347 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1349 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \  argument
1350 	MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1352 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \  argument
1353 	MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1355 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1357 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1359 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1360 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1362 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1363 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1365 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1366 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1368 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1369 	MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1371 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1372 		MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1374 #define MLX5_CAP_ESW(mdev, cap) \  argument
1376 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1378 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1380 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1382 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1384 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1386 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1388 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1390 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1392 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1394 #define MLX5_CAP_ADV_RDMA(mdev, cap) \  argument
1396 		 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1398 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1399 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1401 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1402 	MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1404 #define MLX5_CAP_ODP(mdev, cap)\  argument
1405 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1407 #define MLX5_CAP_ODP_SCHEME(mdev, cap)                                \  argument
1411 			  memory_page_fault_scheme_cap.cap) :         \
1413 			  transport_page_fault_scheme_cap.cap))
1415 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1416 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1418 #define MLX5_CAP_QOS(mdev, cap)\  argument
1419 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1421 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1422 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1451 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1452 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1454 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1455 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1457 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1458 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1460 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1461 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1463 #define MLX5_CAP_TLS(mdev, cap) \  argument
1464 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1466 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1467 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1469 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1471 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1473 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1475 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1477 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1478 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1480 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1481 	MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1483 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1484 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1486 #define MLX5_CAP_SHAMPO(mdev, cap) \  argument
1487 	MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)