1287 #define MLX5_CAP_GEN(mdev, cap) \  argument
1290 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1293 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1296 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1299 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1302 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1305 #define MLX5_CAP_ETH(mdev, cap) \  argument
1309 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1313 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1316 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1319 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1322 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1325 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1328 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1331 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1334 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1337 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1340 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1343 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1346 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1349 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \  argument
1352 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \  argument
1355 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1359 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1362 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1365 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1368 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1371 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1374 #define MLX5_CAP_ESW(mdev, cap) \  argument
1378 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1382 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1386 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1390 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1394 #define MLX5_CAP_ADV_RDMA(mdev, cap) \  argument
1398 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1401 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1404 #define MLX5_CAP_ODP(mdev, cap)\  argument
1407 #define MLX5_CAP_ODP_SCHEME(mdev, cap)                                \  argument
1415 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1418 #define MLX5_CAP_QOS(mdev, cap)\  argument
1421 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1451 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1454 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1457 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1460 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1463 #define MLX5_CAP_TLS(mdev, cap) \  argument
1466 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1469 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1473 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1477 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1480 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1483 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1486 #define MLX5_CAP_SHAMPO(mdev, cap) \  argument