Lines Matching +full:stm32 +full:- +full:timer +full:- +full:counter
1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/dma-mapping.h>
24 #define TIM_CNT 0x24 /* Counter */
26 #define TIM_ARR 0x2c /* Auto-Reload Register */
27 #define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */
32 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
40 #define TIM_CR1_CEN BIT(0) /* Counter Enable */
41 #define TIM_CR1_DIR BIT(4) /* Counter Direction */
42 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
48 #define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */
54 #define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */
78 #define TIM_CCER_CCxE(x) BIT(0 + 4 * ((x) - 1)) /* Capt/Comp x out Ena (x ∈ {1, .. 4}) */
79 #define TIM_CCER_CCxP(x) BIT(1 + 4 * ((x) - 1)) /* Capt/Comp x Polarity (x ∈ {1, .. 4}) */
80 #define TIM_CCER_CCxNE(x) BIT(2 + 4 * ((x) - 1)) /* Capt/Comp xN out Ena (x ∈ {1, .. 4}) */
81 #define TIM_CCER_CCxNP(x) BIT(3 + 4 * ((x) - 1)) /* Capt/Comp xN Polarity (x ∈ {1, .. 4}) */
107 #define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */
108 #define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */
135 /* STM32 Timer may have either a unique global interrupt or 4 interrupt lines */
145 * struct stm32_timers_dma - STM32 timer DMA handling.
150 * @chans: DMA channels available for this timer instance
183 return -ENODEV; in stm32_timers_dma_burst_read()