Lines Matching +full:architecturally +full:- +full:defined
1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Peripheral id registers (0xFD0-0xFEC) */
26 /* Component id registers (0xFF0-0xFFC) */
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
82 * @link_subtype: type of link this component is, as defined
84 * @source_subtype: type of source this component is, as defined
86 * @helper_subtype: type of helper this component is, as defined
100 * struct coresight_platform_data - data harvested from the firmware
119 * struct csdev_access - Abstraction of a CoreSight device access.
145 * struct coresight_desc - description of a component required from drivers
146 * @type: as defined by @coresight_dev_type.
147 * @subtype: as defined by @coresight_dev_subtype.
148 * @ops: generic operations for this component, as defined
153 * in the component's sysfs sub-directory.
169 * struct coresight_connection - representation of a single connection
183 * +-----------------------------+ +-----------------------------+
185 * |-----------------------------| |-----------------------------|
187 * | | | dest_dev*|<--
188 * |pdata->out_conns[nr_outconns]|<->|src_dev* | |
190 * +-----------------------------+ +-----------------------------+ |
192 * +-----------------------------+ |
194 * |------------------------------ |
196 * | pdata->in_conns[nr_inconns]|<--
198 * +-----------------------------+
214 * struct coresight_sysfs_link - representation of a connection in sysfs.
216 * @orig_name: Name to use for the link orig->target.
218 * @target_name: Name to use for the link target->orig.
227 /* architecturally we have 128 IDs some of which are reserved */
246 * struct coresight_device - representation of a device as used by the framework
248 * @type: as defined by @coresight_dev_type.
249 * @subtype: as defined by @coresight_dev_subtype.
250 * @ops: generic operations for this component, as defined
258 * a non-atomic read would also work. This is the main point of
310 * coresight_dev_list - Mapping for devices to "name" index for device
334 * struct coresight_path - data needed by enable/disable path
349 #define coresight_ops(csdev) csdev->ops
350 #define source_ops(csdev) csdev->ops->source_ops
351 #define sink_ops(csdev) csdev->ops->sink_ops
352 #define link_ops(csdev) csdev->ops->link_ops
353 #define helper_ops(csdev) csdev->ops->helper_ops
354 #define ect_ops(csdev) csdev->ops->ect_ops
355 #define panic_ops(csdev) csdev->ops->panic_ops
358 * struct coresight_ops_sink - basic operations for a sink
380 * struct coresight_ops_link - basic operations for a link
395 * struct coresight_ops_source - basic operations for a source
411 * struct coresight_ops_helper - Operations for a helper device.
427 * struct coresight_ops_panic - Generic device ops for panic handing
448 if (likely(csa->io_mem)) in csdev_access_relaxed_read32()
449 return readl_relaxed(csa->base + offset); in csdev_access_relaxed_read32()
451 return csa->read(offset, true, false); in csdev_access_relaxed_read32()
478 * clk - Clock is found and enabled
479 * NULL - clock is not found
480 * ERROR - Clock is found but failed to enable
517 if (likely(csa->io_mem)) { in csdev_access_relaxed_read_pair()
518 return readl_relaxed(csa->base + lo_offset) | in csdev_access_relaxed_read_pair()
519 ((u64)readl_relaxed(csa->base + hi_offset) << 32); in csdev_access_relaxed_read_pair()
522 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); in csdev_access_relaxed_read_pair()
528 if (likely(csa->io_mem)) { in csdev_access_relaxed_write_pair()
529 writel_relaxed((u32)val, csa->base + lo_offset); in csdev_access_relaxed_write_pair()
530 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); in csdev_access_relaxed_write_pair()
532 csa->write((u32)val, lo_offset, true, false); in csdev_access_relaxed_write_pair()
533 csa->write((u32)(val >> 32), hi_offset, true, false); in csdev_access_relaxed_write_pair()
539 if (likely(csa->io_mem)) in csdev_access_read32()
540 return readl(csa->base + offset); in csdev_access_read32()
542 return csa->read(offset, false, false); in csdev_access_read32()
548 if (likely(csa->io_mem)) in csdev_access_relaxed_write32()
549 writel_relaxed(val, csa->base + offset); in csdev_access_relaxed_write32()
551 csa->write(val, offset, true, false); in csdev_access_relaxed_write32()
556 if (likely(csa->io_mem)) in csdev_access_write32()
557 writel(val, csa->base + offset); in csdev_access_write32()
559 csa->write(val, offset, false, false); in csdev_access_write32()
567 if (likely(csa->io_mem)) in csdev_access_relaxed_read64()
568 return readq_relaxed(csa->base + offset); in csdev_access_relaxed_read64()
570 return csa->read(offset, true, true); in csdev_access_relaxed_read64()
575 if (likely(csa->io_mem)) in csdev_access_read64()
576 return readq(csa->base + offset); in csdev_access_read64()
578 return csa->read(offset, false, true); in csdev_access_read64()
584 if (likely(csa->io_mem)) in csdev_access_relaxed_write64()
585 writeq_relaxed(val, csa->base + offset); in csdev_access_relaxed_write64()
587 csa->write(val, offset, true, true); in csdev_access_relaxed_write64()
592 if (likely(csa->io_mem)) in csdev_access_write64()
593 writeq(val, csa->base + offset); in csdev_access_write64()
595 csa->write(val, offset, false, true); in csdev_access_write64()
627 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE); in coresight_is_device_source()
633 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); in coresight_is_percpu_source()
638 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && in coresight_is_percpu_sink()
639 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); in coresight_is_percpu_sink()
649 return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == in coresight_take_mode()
655 return local_read(&csdev->mode); in coresight_get_mode()
671 local_set(&csdev->mode, new_mode); in coresight_set_mode()