mmp/hw/mmp_ctrl.h

1054 struct dsi_regs {  struct
1057 	u32 ctrl0;
1058 	u32 ctrl1;
1059 	u32 reserved1[2];
1060 	u32 irq_status;
1061 	u32 irq_mask;
1062 	u32 reserved2[2];
1068 	u32 cmd0;
1069 	u32 cmd1;
1070 	u32 cmd2;
1071 	u32 cmd3;
1072 	u32 dat0;
1073 	u32 status0;
1074 	u32 status1;
1075 	u32 status2;
1076 	u32 status3;
1077 	u32 status4;
1078 	u32 reserved3[2];
1080 	u32 smt_cmd;
1081 	u32 smt_ctrl0;
1082 	u32 smt_ctrl1;
1083 	u32 reserved4[1];
1085 	u32 rx0_status;
1089 	u32 rx0_header;
1090 	u32 rx1_status;
1091 	u32 rx1_header;
1092 	u32 rx_ctrl;
1093 	u32 rx_ctrl1;
1094 	u32 rx2_status;
1095 	u32 rx2_header;
1096 	u32 reserved5[1];
1098 	u32 phy_ctrl1;
1101 	u32 phy_ctrl2;
1102 	u32 phy_ctrl3;
1103 	u32 phy_status0;
1104 	u32 phy_status1;
1105 	u32 reserved6[5];
1106 	u32 phy_status2;
1109 	u32 phy_rcomp0;
1110 	u32 reserved7[3];
1117 	u32 phy_timing0;
1118 	u32 phy_timing1;
1119 	u32 phy_timing2;
1120 	u32 phy_timing3;
1121 	u32 phy_code_0;
1122 	u32 phy_code_1;
1123 	u32 reserved8[2];
1124 	u32 mem_ctrl;
1125 	u32 tx_timer;
1126 	u32 rx_timer;
1127 	u32 turn_timer;
1128 	u32 reserved9[4];
1139 	struct dsi_lcd_regs lcd1;
1140 	u32 reserved10[11];
1141 	struct dsi_lcd_regs lcd2;