Lines Matching +full:addr +full:- +full:mode
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
18 #include <linux/dma-mapping.h>
31 * dwc2_backup_global_registers() - Backup global controller registers.
41 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
44 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
46 gr->gintsts = dwc2_readl(hsotg, GINTSTS); in dwc2_backup_global_registers()
47 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
48 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); in dwc2_backup_global_registers()
49 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); in dwc2_backup_global_registers()
50 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); in dwc2_backup_global_registers()
51 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); in dwc2_backup_global_registers()
52 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); in dwc2_backup_global_registers()
53 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); in dwc2_backup_global_registers()
54 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); in dwc2_backup_global_registers()
55 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); in dwc2_backup_global_registers()
56 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); in dwc2_backup_global_registers()
57 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); in dwc2_backup_global_registers()
59 gr->valid = true; in dwc2_backup_global_registers()
64 * dwc2_restore_global_registers() - Restore controller global registers.
74 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_global_registers()
77 gr = &hsotg->gr_backup; in dwc2_restore_global_registers()
78 if (!gr->valid) { in dwc2_restore_global_registers()
79 dev_err(hsotg->dev, "%s: no global registers to restore\n", in dwc2_restore_global_registers()
81 return -EINVAL; in dwc2_restore_global_registers()
83 gr->valid = false; in dwc2_restore_global_registers()
86 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); in dwc2_restore_global_registers()
87 dwc2_writel(hsotg, gr->gintmsk, GINTMSK); in dwc2_restore_global_registers()
88 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); in dwc2_restore_global_registers()
89 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); in dwc2_restore_global_registers()
90 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); in dwc2_restore_global_registers()
91 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); in dwc2_restore_global_registers()
92 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); in dwc2_restore_global_registers()
93 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); in dwc2_restore_global_registers()
94 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); in dwc2_restore_global_registers()
95 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); in dwc2_restore_global_registers()
96 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); in dwc2_restore_global_registers()
102 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
113 gr = &hsotg->gr_backup; in dwc2_exit_partial_power_down()
116 * Restore host or device regisers with the same mode core enterted in dwc2_exit_partial_power_down()
120 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) in dwc2_exit_partial_power_down()
128 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
141 * dwc2_restore_essential_regs() - Restore essiential regs of core.
144 * @rmode: Restore mode, enabled in case of remote-wakeup.
145 * @is_host: Host or device mode.
155 gr = &hsotg->gr_backup; in dwc2_restore_essential_regs()
156 dr = &hsotg->dr_backup; in dwc2_restore_essential_regs()
157 hr = &hsotg->hr_backup; in dwc2_restore_essential_regs()
159 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); in dwc2_restore_essential_regs()
162 pcgcctl = (gr->pcgcctl & 0xffffc000); in dwc2_restore_essential_regs()
174 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); in dwc2_restore_essential_regs()
183 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); in dwc2_restore_essential_regs()
186 dwc2_writel(hsotg, hr->hcfg, HCFG); in dwc2_restore_essential_regs()
196 dwc2_writel(hsotg, dr->dcfg, DCFG); in dwc2_restore_essential_regs()
209 * dwc2_hib_restore_common() - Common part of restore routine.
212 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
213 * @is_host: Host or device mode.
220 /* Switch-on voltage to the core */ in dwc2_hib_restore_common()
273 dev_dbg(hsotg->dev, in dwc2_hib_restore_common()
277 dev_dbg(hsotg->dev, "restore done generated here\n"); in dwc2_hib_restore_common()
288 * dwc2_wait_for_mode() - Waits for the controller mode.
290 * @host_mode: If true, waits for host mode, otherwise device mode.
299 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", in dwc2_wait_for_mode()
308 dev_vdbg(hsotg->dev, "%s mode set\n", in dwc2_wait_for_mode()
317 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", in dwc2_wait_for_mode()
327 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
361 * dwc2_enter_hibernation() - Common function to enter hibernation.
364 * @is_host: True if core is in host mode.
377 * dwc2_exit_hibernation() - Common function to exit from hibernation.
380 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
382 * @is_host: True if core is in host mode.
404 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_core_reset()
407 * If the current mode is host, either due to the force mode in dwc2_core_reset()
410 * the mode to device. A delay from the IDDIG debounce filter in dwc2_core_reset()
411 * will occur before going back to host mode. in dwc2_core_reset()
413 * Determine whether we will go back into host mode after a in dwc2_core_reset()
431 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) < in dwc2_core_reset()
435 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n", in dwc2_core_reset()
437 return -EBUSY; in dwc2_core_reset()
442 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n", in dwc2_core_reset()
444 return -EBUSY; in dwc2_core_reset()
453 * Switching from device mode to host mode by disconnecting in dwc2_core_reset()
458 * if in host mode we disconnect the micro a to b host in dwc2_core_reset()
464 * mode. in dwc2_core_reset()
470 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n", in dwc2_core_reset()
472 return -EBUSY; in dwc2_core_reset()
482 * dwc2_force_mode() - Force the mode of the controller.
484 * Forcing the mode is needed for two cases:
487 * controller to stay in a particular mode regardless of ID pin
492 * device mode. We may need to force the mode if the current mode does
493 * not allow us to access the register in the mode that we want.
495 * In either case it only makes sense to force the mode if the
502 * the filter is configured and enabled. We poll the current mode of
506 * @host: Host mode flag
514 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); in dwc2_force_mode()
517 * Force mode has no effect if the hardware is not OTG. in dwc2_force_mode()
524 * need to ever force the mode to the opposite mode. in dwc2_force_mode()
526 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) in dwc2_force_mode()
529 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) in dwc2_force_mode()
546 * dwc2_clear_force_mode() - Clears the force mode bits.
551 * the force mode. We only need to call this once during probe if
563 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); in dwc2_clear_force_mode()
575 * Sets or clears force mode based on the dr_mode parameter.
579 switch (hsotg->dr_mode) { in dwc2_force_dr_mode()
583 * platforms on their host-only dwc2. in dwc2_force_dr_mode()
596 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", in dwc2_force_dr_mode()
597 __func__, hsotg->dr_mode); in dwc2_force_dr_mode()
603 * dwc2_enable_acg - enable active clock gating feature
607 if (hsotg->params.acg_enable) { in dwc2_enable_acg()
610 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); in dwc2_enable_acg()
617 * dwc2_dump_host_registers() - Prints the host registers
627 u32 __iomem *addr; in dwc2_dump_host_registers() local
630 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
631 addr = hsotg->regs + HCFG; in dwc2_dump_host_registers()
632 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
633 (unsigned long)addr, dwc2_readl(hsotg, HCFG)); in dwc2_dump_host_registers()
634 addr = hsotg->regs + HFIR; in dwc2_dump_host_registers()
635 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
636 (unsigned long)addr, dwc2_readl(hsotg, HFIR)); in dwc2_dump_host_registers()
637 addr = hsotg->regs + HFNUM; in dwc2_dump_host_registers()
638 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
639 (unsigned long)addr, dwc2_readl(hsotg, HFNUM)); in dwc2_dump_host_registers()
640 addr = hsotg->regs + HPTXSTS; in dwc2_dump_host_registers()
641 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
642 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS)); in dwc2_dump_host_registers()
643 addr = hsotg->regs + HAINT; in dwc2_dump_host_registers()
644 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
645 (unsigned long)addr, dwc2_readl(hsotg, HAINT)); in dwc2_dump_host_registers()
646 addr = hsotg->regs + HAINTMSK; in dwc2_dump_host_registers()
647 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
648 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK)); in dwc2_dump_host_registers()
649 if (hsotg->params.dma_desc_enable) { in dwc2_dump_host_registers()
650 addr = hsotg->regs + HFLBADDR; in dwc2_dump_host_registers()
651 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
652 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR)); in dwc2_dump_host_registers()
655 addr = hsotg->regs + HPRT0; in dwc2_dump_host_registers()
656 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
657 (unsigned long)addr, dwc2_readl(hsotg, HPRT0)); in dwc2_dump_host_registers()
659 for (i = 0; i < hsotg->params.host_channels; i++) { in dwc2_dump_host_registers()
660 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
661 addr = hsotg->regs + HCCHAR(i); in dwc2_dump_host_registers()
662 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
663 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i))); in dwc2_dump_host_registers()
664 addr = hsotg->regs + HCSPLT(i); in dwc2_dump_host_registers()
665 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
666 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i))); in dwc2_dump_host_registers()
667 addr = hsotg->regs + HCINT(i); in dwc2_dump_host_registers()
668 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
669 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i))); in dwc2_dump_host_registers()
670 addr = hsotg->regs + HCINTMSK(i); in dwc2_dump_host_registers()
671 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
672 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i))); in dwc2_dump_host_registers()
673 addr = hsotg->regs + HCTSIZ(i); in dwc2_dump_host_registers()
674 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
675 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i))); in dwc2_dump_host_registers()
676 addr = hsotg->regs + HCDMA(i); in dwc2_dump_host_registers()
677 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
678 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i))); in dwc2_dump_host_registers()
679 if (hsotg->params.dma_desc_enable) { in dwc2_dump_host_registers()
680 addr = hsotg->regs + HCDMAB(i); in dwc2_dump_host_registers()
681 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
682 (unsigned long)addr, dwc2_readl(hsotg, in dwc2_dump_host_registers()
690 * dwc2_dump_global_registers() - Prints the core global registers
700 u32 __iomem *addr; in dwc2_dump_global_registers() local
702 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
703 addr = hsotg->regs + GOTGCTL; in dwc2_dump_global_registers()
704 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
705 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL)); in dwc2_dump_global_registers()
706 addr = hsotg->regs + GOTGINT; in dwc2_dump_global_registers()
707 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
708 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT)); in dwc2_dump_global_registers()
709 addr = hsotg->regs + GAHBCFG; in dwc2_dump_global_registers()
710 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
711 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG)); in dwc2_dump_global_registers()
712 addr = hsotg->regs + GUSBCFG; in dwc2_dump_global_registers()
713 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
714 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG)); in dwc2_dump_global_registers()
715 addr = hsotg->regs + GRSTCTL; in dwc2_dump_global_registers()
716 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
717 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL)); in dwc2_dump_global_registers()
718 addr = hsotg->regs + GINTSTS; in dwc2_dump_global_registers()
719 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
720 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS)); in dwc2_dump_global_registers()
721 addr = hsotg->regs + GINTMSK; in dwc2_dump_global_registers()
722 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
723 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK)); in dwc2_dump_global_registers()
724 addr = hsotg->regs + GRXSTSR; in dwc2_dump_global_registers()
725 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
726 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR)); in dwc2_dump_global_registers()
727 addr = hsotg->regs + GRXFSIZ; in dwc2_dump_global_registers()
728 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
729 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ)); in dwc2_dump_global_registers()
730 addr = hsotg->regs + GNPTXFSIZ; in dwc2_dump_global_registers()
731 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
732 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ)); in dwc2_dump_global_registers()
733 addr = hsotg->regs + GNPTXSTS; in dwc2_dump_global_registers()
734 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
735 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS)); in dwc2_dump_global_registers()
736 addr = hsotg->regs + GI2CCTL; in dwc2_dump_global_registers()
737 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
738 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL)); in dwc2_dump_global_registers()
739 addr = hsotg->regs + GPVNDCTL; in dwc2_dump_global_registers()
740 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
741 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL)); in dwc2_dump_global_registers()
742 addr = hsotg->regs + GGPIO; in dwc2_dump_global_registers()
743 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
744 (unsigned long)addr, dwc2_readl(hsotg, GGPIO)); in dwc2_dump_global_registers()
745 addr = hsotg->regs + GUID; in dwc2_dump_global_registers()
746 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
747 (unsigned long)addr, dwc2_readl(hsotg, GUID)); in dwc2_dump_global_registers()
748 addr = hsotg->regs + GSNPSID; in dwc2_dump_global_registers()
749 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
750 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID)); in dwc2_dump_global_registers()
751 addr = hsotg->regs + GHWCFG1; in dwc2_dump_global_registers()
752 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
753 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1)); in dwc2_dump_global_registers()
754 addr = hsotg->regs + GHWCFG2; in dwc2_dump_global_registers()
755 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
756 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2)); in dwc2_dump_global_registers()
757 addr = hsotg->regs + GHWCFG3; in dwc2_dump_global_registers()
758 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
759 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3)); in dwc2_dump_global_registers()
760 addr = hsotg->regs + GHWCFG4; in dwc2_dump_global_registers()
761 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
762 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4)); in dwc2_dump_global_registers()
763 addr = hsotg->regs + GLPMCFG; in dwc2_dump_global_registers()
764 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
765 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG)); in dwc2_dump_global_registers()
766 addr = hsotg->regs + GPWRDN; in dwc2_dump_global_registers()
767 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
768 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN)); in dwc2_dump_global_registers()
769 addr = hsotg->regs + GDFIFOCFG; in dwc2_dump_global_registers()
770 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
771 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG)); in dwc2_dump_global_registers()
772 addr = hsotg->regs + HPTXFSIZ; in dwc2_dump_global_registers()
773 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
774 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ)); in dwc2_dump_global_registers()
776 addr = hsotg->regs + PCGCTL; in dwc2_dump_global_registers()
777 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
778 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL)); in dwc2_dump_global_registers()
783 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
792 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); in dwc2_flush_tx_fifo()
796 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", in dwc2_flush_tx_fifo()
804 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", in dwc2_flush_tx_fifo()
812 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
820 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_flush_rx_fifo()
824 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", in dwc2_flush_rx_fifo()
832 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n", in dwc2_flush_rx_fifo()
848 * dwc2_enable_global_interrupts() - Enables the controller's Global
862 * dwc2_disable_global_interrupts() - Disables the controller's Global
894 /* Returns true if the controller is host-only. */
903 /* Returns true if the controller is device-only. */
913 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
919 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
932 return -ETIMEDOUT; in dwc2_hsotg_wait_bit_set()
936 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
942 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
955 return -ETIMEDOUT; in dwc2_hsotg_wait_bit_clear()
966 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_init_fs_ls_pclk_sel()
967 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_init_fs_ls_pclk_sel()
968 hsotg->params.ulpi_fs_ls) || in dwc2_init_fs_ls_pclk_sel()
969 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_init_fs_ls_pclk_sel()
977 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
998 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI && in dwc2_set_clock_switch_timer()
999 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || in dwc2_set_clock_switch_timer()
1000 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_set_clock_switch_timer()
1001 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || in dwc2_set_clock_switch_timer()
1002 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && in dwc2_set_clock_switch_timer()
1003 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED)) { in dwc2_set_clock_switch_timer()
1007 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW && in dwc2_set_clock_switch_timer()
1008 hsotg->hw_params.hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && in dwc2_set_clock_switch_timer()
1009 hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) { in dwc2_set_clock_switch_timer()
1029 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
1042 dev_err(hsotg->dev, in dwc2_fs_phy_init()
1048 if (hsotg->params.activate_stm_fs_transceiver) { in dwc2_fs_phy_init()
1051 dev_dbg(hsotg->dev, "Activating transceiver\n"); in dwc2_fs_phy_init()
1064 * do this on HNP Dev/Host mode switches (done in dev_init and in dwc2_fs_phy_init()
1070 if (hsotg->params.i2c_enable) { in dwc2_fs_phy_init()
1071 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
1107 switch (hsotg->params.phy_type) { in dwc2_hs_phy_init()
1110 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
1113 if (hsotg->params.phy_ulpi_ddr) in dwc2_hs_phy_init()
1117 if (hsotg->params.oc_disable) in dwc2_hs_phy_init()
1123 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
1125 if (hsotg->params.phy_utmi_width == 16) in dwc2_hs_phy_init()
1129 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); in dwc2_hs_phy_init()
1139 dev_err(hsotg->dev, in dwc2_hs_phy_init()
1152 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI) in dwc2_set_turnaround_time()
1158 if (hsotg->params.phy_utmi_width == 16) in dwc2_set_turnaround_time()
1172 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || in dwc2_phy_init()
1173 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && in dwc2_phy_init()
1174 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { in dwc2_phy_init()
1175 /* If FS/LS mode with FS/LS PHY */ in dwc2_phy_init()
1189 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && in dwc2_phy_init()
1190 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && in dwc2_phy_init()
1191 hsotg->params.ulpi_fs_ls) { in dwc2_phy_init()
1192 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()
1204 if (!hsotg->params.activate_ingenic_overcurrent_detection) { in dwc2_phy_init()
1206 otgctl = readl(hsotg->regs + GOTGCTL); in dwc2_phy_init()
1208 writel(otgctl, hsotg->regs + GOTGCTL); in dwc2_phy_init()