Lines Matching +full:0 +full:x2000
27 DBG_INIT = 0x01,
28 DBG_BASIC = 0x02,
29 DBG_CORE = 0x04,
30 DBG_OPEN = 0x08,
31 DBG_CLOSE = 0x10,
32 DBG_READ = 0x20,
33 DBG_WRITE = 0x40,
34 DBG_IOCTL = 0x80,
35 DBG_PROC = 0x100,
36 DBG_PARAM = 0x200,
37 DBG_PSCAN = 0x400,
38 DBG_EVENT = 0x800,
39 DBG_DRAIN = 0x1000,
40 DBG_MSIGS = 0x2000,
41 DBG_MGMT = 0x4000,
42 DBG_INTR = 0x8000,
43 DBG_CARR = 0x10000,
50 } while (0)
57 #define PCI_DEVICE_ID_CLASSIC_4 0x0028
58 #define PCI_DEVICE_ID_CLASSIC_8 0x0029
59 #define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0
60 #define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1
61 #define PCI_DEVICE_ID_NEO_4 0x00B0
62 #define PCI_DEVICE_ID_NEO_1_422 0x00CC
63 #define PCI_DEVICE_ID_NEO_1_422_485 0x00CD
64 #define PCI_DEVICE_ID_NEO_2_422_485 0x00CE
65 #define PCIE_DEVICE_ID_NEO_8 0x00F0
66 #define PCIE_DEVICE_ID_NEO_4 0x00F1
67 #define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2
68 #define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3
78 #define BD_RUNNING 0x0
79 #define BD_REASON 0x7f
80 #define BD_NOTFOUND 0x1
81 #define BD_NOIOPORT 0x2
82 #define BD_NOMEM 0x3
83 #define BD_NOBIOS 0x4
84 #define BD_NOFEP 0x5
85 #define BD_FAILED 0x6
86 #define BD_ALLOCATED 0x7
87 #define BD_TRIBOOT 0x8
88 #define BD_BADKME 0x80
126 int boardnum; /* Board number: 0-32 */
160 #define CH_PRON 0x0001 /* Printer on string */
161 #define CH_STOP 0x0002 /* Output is stopped */
162 #define CH_STOPI 0x0004 /* Input is stopped */
163 #define CH_CD 0x0008 /* Carrier is present */
164 #define CH_FCAR 0x0010 /* Carrier forced on */
165 #define CH_HANGUP 0x0020 /* Hangup received */
167 #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
168 #define CH_OPENING 0x0080 /* Port in fragile open state */
169 #define CH_CLOSING 0x0100 /* Port in fragile close state */
170 #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
171 #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
172 #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
173 #define CH_BREAK_SENDING 0x1000 /* Break is being sent */
174 #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
175 #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
178 #define RQUEUEMASK 0x1FFF /* 8 K - 1 */
179 #define EQUEUEMASK 0x1FFF /* 8 K - 1 */
194 u32 ch_portnum; /* Port number, 0 offset. */
266 #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
268 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
270 #define UART_16654_FCR_TXTRIGGER_8 0x0
271 #define UART_16654_FCR_TXTRIGGER_16 0x10
272 #define UART_16654_FCR_TXTRIGGER_32 0x20
273 #define UART_16654_FCR_TXTRIGGER_56 0x30
275 #define UART_16654_FCR_RXTRIGGER_8 0x0
276 #define UART_16654_FCR_RXTRIGGER_16 0x40
277 #define UART_16654_FCR_RXTRIGGER_56 0x80
278 #define UART_16654_FCR_RXTRIGGER_60 0xC0
280 #define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
281 #define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
287 #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
288 #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
289 #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
290 #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
291 #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
293 #define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
294 #define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
296 #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
297 #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
298 #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
327 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
329 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
334 #define UART_17158_POLL_ADDR_OFFSET 0x80
342 #define UART_17158_FCTR_RTS_NODELAY 0x00
343 #define UART_17158_FCTR_RTS_4DELAY 0x01
344 #define UART_17158_FCTR_RTS_6DELAY 0x02
345 #define UART_17158_FCTR_RTS_8DELAY 0x03
346 #define UART_17158_FCTR_RTS_12DELAY 0x12
347 #define UART_17158_FCTR_RTS_16DELAY 0x05
348 #define UART_17158_FCTR_RTS_20DELAY 0x13
349 #define UART_17158_FCTR_RTS_24DELAY 0x06
350 #define UART_17158_FCTR_RTS_28DELAY 0x14
351 #define UART_17158_FCTR_RTS_32DELAY 0x07
352 #define UART_17158_FCTR_RTS_36DELAY 0x16
353 #define UART_17158_FCTR_RTS_40DELAY 0x08
354 #define UART_17158_FCTR_RTS_44DELAY 0x09
355 #define UART_17158_FCTR_RTS_48DELAY 0x10
356 #define UART_17158_FCTR_RTS_52DELAY 0x11
358 #define UART_17158_FCTR_RTS_IRDA 0x10
359 #define UART_17158_FCTR_RS485 0x20
360 #define UART_17158_FCTR_TRGA 0x00
361 #define UART_17158_FCTR_TRGB 0x40
362 #define UART_17158_FCTR_TRGC 0x80
363 #define UART_17158_FCTR_TRGD 0xC0
366 #define UART_17158_FCTR_BIT6 0x40
367 #define UART_17158_FCTR_BIT7 0x80
374 #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
375 #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
376 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
377 #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
383 #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
384 #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
385 #define UART_17158_TXRDY 0x3 /* TX Ready */
386 #define UART_17158_MSR 0x4 /* Modem State Change */
387 #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
388 #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
394 #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
395 #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
396 #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
397 #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
398 #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
400 #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
401 #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
403 #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
404 #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
405 #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
406 #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */