115 	struct clk		*gclk;		/* uart generic clock */  member
2092 		if (__clk_is_enabled(atmel_port->gclk))  in atmel_serial_pm()
2093 			clk_disable_unprepare(atmel_port->gclk);  in atmel_serial_pm()
2287 	 * if we use the GCLK as the clock source driving the baudrate  in atmel_set_termios()
2291 		if (__clk_is_enabled(atmel_port->gclk))  in atmel_set_termios()
2292 			clk_disable_unprepare(atmel_port->gclk);  in atmel_set_termios()
2293 		gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);  in atmel_set_termios()
2297 			clk_set_rate(atmel_port->gclk, 16 * baud);  in atmel_set_termios()
2298 			ret = clk_prepare_enable(atmel_port->gclk);  in atmel_set_termios()
2310 			 * Set the Clock Divisor for GCLK to 1.  in atmel_set_termios()
2906 	atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");  in atmel_serial_probe()
2907 	if (IS_ERR(atmel_port->gclk)) {  in atmel_serial_probe()
2908 		ret = PTR_ERR(atmel_port->gclk);  in atmel_serial_probe()