Lines Matching +full:zynq +full:- +full:gpio +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
36 #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
57 * QSPI Configuration Register - Baud rate and target select
109 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
121 * struct zynq_qspi - Defines qspi driver instance
151 return readl_relaxed(xqspi->regs + offset); in zynq_qspi_read()
157 writel_relaxed(val, xqspi->regs + offset); in zynq_qspi_write()
161 * zynq_qspi_init_hw - Initialize the hardware
167 * - Host mode
168 * - Baud rate divisor is set to 2
169 * - Tx threshold set to 1l Rx threshold set to 32
170 * - Flash memory interface mode enabled
171 * - Size of the word to be transferred as 8 bit
173 * - Disable and clear all the interrupts
174 * - Enable manual target select
175 * - Enable manual start
176 * - Deselect all the chip select lines
177 * - Set the size of the word to be transferred as 32 bit
178 * - Set the little endian mode of TX FIFO and
179 * - Enable the QSPI controller
190 /* At the same time, enable dual mode if more than 1 CS is available */ in zynq_qspi_init_hw()
191 if (num_cs > 1) in zynq_qspi_init_hw()
234 if (op->addr.nbytes > 3) in zynq_qspi_supports_op()
241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
243 * @size: Number of bytes to be read (1..4)
251 if (xqspi->rxbuf) { in zynq_qspi_rxfifo_op()
252 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size); in zynq_qspi_rxfifo_op()
253 xqspi->rxbuf += size; in zynq_qspi_rxfifo_op()
256 xqspi->rx_bytes -= size; in zynq_qspi_rxfifo_op()
257 if (xqspi->rx_bytes < 0) in zynq_qspi_rxfifo_op()
258 xqspi->rx_bytes = 0; in zynq_qspi_rxfifo_op()
262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
264 * @size: Number of bytes to be written (1..4)
273 if (xqspi->txbuf) { in zynq_qspi_txfifo_op()
275 memcpy(&data, xqspi->txbuf, size); in zynq_qspi_txfifo_op()
276 xqspi->txbuf += size; in zynq_qspi_txfifo_op()
281 xqspi->tx_bytes -= size; in zynq_qspi_txfifo_op()
282 zynq_qspi_write(xqspi, offset[size - 1], data); in zynq_qspi_txfifo_op()
286 * zynq_qspi_chipselect - Select or deselect the chip select line
288 * @assert: 1 for select or 0 for deselect the chip select line
292 struct spi_controller *ctlr = spi->controller; in zynq_qspi_chipselect()
297 if (ctlr->num_chipselect > 1) { in zynq_qspi_chipselect()
318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
326 * Return: 0 on success and -EINVAL on invalid input parameter
344 * i.e. 000 - divide by 2 in zynq_qspi_config_op()
345 * 001 - divide by 4 in zynq_qspi_config_op()
346 * ---------------- in zynq_qspi_config_op()
347 * 111 - divide by 256 in zynq_qspi_config_op()
350 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > in zynq_qspi_config_op()
351 op->max_freq) in zynq_qspi_config_op()
359 if (spi->mode & SPI_CPHA) in zynq_qspi_config_op()
361 if (spi->mode & SPI_CPOL) in zynq_qspi_config_op()
372 * zynq_qspi_setup_op - Configure the QSPI controller
382 struct spi_controller *ctlr = spi->controller; in zynq_qspi_setup_op()
386 if (ctlr->busy) in zynq_qspi_setup_op()
387 return -EBUSY; in zynq_qspi_setup_op()
389 ret = clk_enable(qspi->refclk); in zynq_qspi_setup_op()
393 ret = clk_enable(qspi->pclk); in zynq_qspi_setup_op()
395 clk_disable(qspi->refclk); in zynq_qspi_setup_op()
406 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
416 len = xqspi->tx_bytes; in zynq_qspi_write_op()
432 if (xqspi->txbuf) { in zynq_qspi_write_op()
433 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET, in zynq_qspi_write_op()
434 xqspi->txbuf, count); in zynq_qspi_write_op()
435 xqspi->txbuf += count * 4; in zynq_qspi_write_op()
438 writel_relaxed(0, xqspi->regs + in zynq_qspi_write_op()
442 xqspi->tx_bytes -= count * 4; in zynq_qspi_write_op()
446 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
454 len = xqspi->rx_bytes - xqspi->tx_bytes; in zynq_qspi_read_op()
458 if (xqspi->rxbuf) { in zynq_qspi_read_op()
459 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET, in zynq_qspi_read_op()
460 xqspi->rxbuf, count); in zynq_qspi_read_op()
461 xqspi->rxbuf += count * 4; in zynq_qspi_read_op()
464 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET); in zynq_qspi_read_op()
466 xqspi->rx_bytes -= count * 4; in zynq_qspi_read_op()
467 len -= count * 4; in zynq_qspi_read_op()
474 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
497 * We have the THRESHOLD value set to 1, in zynq_qspi_irq()
503 if (xqspi->tx_bytes) { in zynq_qspi_irq()
512 if (!xqspi->rx_bytes) { in zynq_qspi_irq()
516 complete(&xqspi->data_completion); in zynq_qspi_irq()
526 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
539 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller); in zynq_qspi_exec_mem_op()
543 zynq_qspi_chipselect(mem->spi, true); in zynq_qspi_exec_mem_op()
544 zynq_qspi_config_op(xqspi, mem->spi, op); in zynq_qspi_exec_mem_op()
546 if (op->cmd.opcode) { in zynq_qspi_exec_mem_op()
547 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
548 xqspi->txbuf = (u8 *)&op->cmd.opcode; in zynq_qspi_exec_mem_op()
549 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
550 xqspi->tx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
551 xqspi->rx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
555 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
557 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
560 if (op->addr.nbytes) { in zynq_qspi_exec_mem_op()
561 for (i = 0; i < op->addr.nbytes; i++) { in zynq_qspi_exec_mem_op()
562 xqspi->txbuf[i] = op->addr.val >> in zynq_qspi_exec_mem_op()
563 (8 * (op->addr.nbytes - i - 1)); in zynq_qspi_exec_mem_op()
566 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
567 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
568 xqspi->tx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
569 xqspi->rx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
573 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
575 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
578 if (op->dummy.nbytes) { in zynq_qspi_exec_mem_op()
579 tmpbuf = kmalloc(op->dummy.nbytes, GFP_KERNEL); in zynq_qspi_exec_mem_op()
581 return -ENOMEM; in zynq_qspi_exec_mem_op()
583 memset(tmpbuf, 0xff, op->dummy.nbytes); in zynq_qspi_exec_mem_op()
584 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
585 xqspi->txbuf = tmpbuf; in zynq_qspi_exec_mem_op()
586 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
587 xqspi->tx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
588 xqspi->rx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
592 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
594 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
599 if (op->data.nbytes) { in zynq_qspi_exec_mem_op()
600 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
601 if (op->data.dir == SPI_MEM_DATA_OUT) { in zynq_qspi_exec_mem_op()
602 xqspi->txbuf = (u8 *)op->data.buf.out; in zynq_qspi_exec_mem_op()
603 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
604 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
605 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
607 xqspi->txbuf = NULL; in zynq_qspi_exec_mem_op()
608 xqspi->rxbuf = (u8 *)op->data.buf.in; in zynq_qspi_exec_mem_op()
609 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
610 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
616 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
618 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
620 zynq_qspi_chipselect(mem->spi, false); in zynq_qspi_exec_mem_op()
635 * zynq_qspi_probe - Probe method for the QSPI driver
646 struct device *dev = &pdev->dev; in zynq_qspi_probe()
647 struct device_node *np = dev->of_node; in zynq_qspi_probe()
651 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi)); in zynq_qspi_probe()
653 return -ENOMEM; in zynq_qspi_probe()
656 xqspi->dev = dev; in zynq_qspi_probe()
658 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); in zynq_qspi_probe()
659 if (IS_ERR(xqspi->regs)) { in zynq_qspi_probe()
660 ret = PTR_ERR(xqspi->regs); in zynq_qspi_probe()
664 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); in zynq_qspi_probe()
665 if (IS_ERR(xqspi->pclk)) { in zynq_qspi_probe()
666 dev_err(&pdev->dev, "pclk clock not found.\n"); in zynq_qspi_probe()
667 ret = PTR_ERR(xqspi->pclk); in zynq_qspi_probe()
671 init_completion(&xqspi->data_completion); in zynq_qspi_probe()
673 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); in zynq_qspi_probe()
674 if (IS_ERR(xqspi->refclk)) { in zynq_qspi_probe()
675 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in zynq_qspi_probe()
676 ret = PTR_ERR(xqspi->refclk); in zynq_qspi_probe()
680 ret = clk_prepare_enable(xqspi->pclk); in zynq_qspi_probe()
682 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); in zynq_qspi_probe()
686 ret = clk_prepare_enable(xqspi->refclk); in zynq_qspi_probe()
688 dev_err(&pdev->dev, "Unable to enable device clock.\n"); in zynq_qspi_probe()
692 xqspi->irq = platform_get_irq(pdev, 0); in zynq_qspi_probe()
693 if (xqspi->irq < 0) { in zynq_qspi_probe()
694 ret = xqspi->irq; in zynq_qspi_probe()
697 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, in zynq_qspi_probe()
698 0, pdev->name, xqspi); in zynq_qspi_probe()
700 ret = -ENXIO; in zynq_qspi_probe()
701 dev_err(&pdev->dev, "request_irq failed\n"); in zynq_qspi_probe()
705 ret = of_property_read_u32(np, "num-cs", in zynq_qspi_probe()
708 ctlr->num_chipselect = 1; in zynq_qspi_probe()
710 ret = -EINVAL; in zynq_qspi_probe()
711 dev_err(&pdev->dev, "only 2 chip selects are available\n"); in zynq_qspi_probe()
714 ctlr->num_chipselect = num_cs; in zynq_qspi_probe()
717 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | in zynq_qspi_probe()
719 ctlr->mem_ops = &zynq_qspi_mem_ops; in zynq_qspi_probe()
720 ctlr->mem_caps = &zynq_qspi_mem_caps; in zynq_qspi_probe()
721 ctlr->setup = zynq_qspi_setup_op; in zynq_qspi_probe()
722 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; in zynq_qspi_probe()
723 ctlr->dev.of_node = np; in zynq_qspi_probe()
726 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect); in zynq_qspi_probe()
728 ret = devm_spi_register_controller(&pdev->dev, ctlr); in zynq_qspi_probe()
730 dev_err(&pdev->dev, "devm_spi_register_controller failed\n"); in zynq_qspi_probe()
737 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_probe()
739 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_probe()
747 * zynq_qspi_remove - Remove method for the QSPI driver
762 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_remove()
763 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_remove()
767 { .compatible = "xlnx,zynq-qspi-1.0", },
774 * zynq_qspi_driver - This structure defines the QSPI platform driver
780 .name = "zynq-qspi",
788 MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");