Lines Matching +full:qpic +full:- +full:spi +full:- +full:nand
2 * SPDX-License-Identifier: GPL-2.0
15 #include <linux/dma-mapping.h>
22 #include <linux/mtd/nand-qpic-common.h>
31 /* QSPI NAND config reg bits */
141 snandc->regs->read_location0 = locreg_val; in qcom_spi_set_read_loc_first()
143 snandc->regs->read_location1 = locreg_val; in qcom_spi_set_read_loc_first()
145 snandc->regs->read_location2 = locreg_val; in qcom_spi_set_read_loc_first()
147 snandc->regs->read_location3 = locreg_val; in qcom_spi_set_read_loc_first()
162 snandc->regs->read_location_last0 = locreg_val; in qcom_spi_set_read_loc_last()
164 snandc->regs->read_location_last1 = locreg_val; in qcom_spi_set_read_loc_last()
166 snandc->regs->read_location_last2 = locreg_val; in qcom_spi_set_read_loc_last()
168 snandc->regs->read_location_last3 = locreg_val; in qcom_spi_set_read_loc_last()
171 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand) in nand_to_qcom_snand() argument
173 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_qcom_snand()
176 return qspi->snandc; in nand_to_qcom_snand()
189 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); in qcom_spi_init()
190 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR); in qcom_spi_init()
191 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT); in qcom_spi_init()
193 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); in qcom_spi_init()
196 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); in qcom_spi_init()
198 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); in qcom_spi_init()
200 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0); in qcom_spi_init()
201 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1, in qcom_spi_init()
206 dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); in qcom_spi_init()
216 struct nand_device *nand = mtd_to_nanddev(mtd); in qcom_spi_ooblayout_ecc() local
217 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ooblayout_ecc()
218 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_ecc()
221 return -ERANGE; in qcom_spi_ooblayout_ecc()
223 oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes; in qcom_spi_ooblayout_ecc()
224 oobregion->offset = mtd->oobsize - oobregion->length; in qcom_spi_ooblayout_ecc()
232 struct nand_device *nand = mtd_to_nanddev(mtd); in qcom_spi_ooblayout_free() local
233 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ooblayout_free()
234 struct qpic_ecc *qecc = snandc->qspi->ecc; in qcom_spi_ooblayout_free()
237 return -ERANGE; in qcom_spi_ooblayout_free()
239 oobregion->length = qecc->steps * 4; in qcom_spi_ooblayout_free()
240 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; in qcom_spi_ooblayout_free()
250 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) in qcom_spi_ecc_init_ctx_pipelined() argument
252 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_init_ctx_pipelined()
253 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in qcom_spi_ecc_init_ctx_pipelined()
254 struct mtd_info *mtd = nanddev_to_mtd(nand); in qcom_spi_ecc_init_ctx_pipelined()
258 cwperpage = mtd->writesize / NANDC_STEP_SIZE; in qcom_spi_ecc_init_ctx_pipelined()
259 snandc->qspi->num_cw = cwperpage; in qcom_spi_ecc_init_ctx_pipelined()
263 return -ENOMEM; in qcom_spi_ecc_init_ctx_pipelined()
264 snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize, in qcom_spi_ecc_init_ctx_pipelined()
266 if (!snandc->qspi->oob_buf) { in qcom_spi_ecc_init_ctx_pipelined()
268 return -ENOMEM; in qcom_spi_ecc_init_ctx_pipelined()
271 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); in qcom_spi_ecc_init_ctx_pipelined()
273 nand->ecc.ctx.priv = ecc_cfg; in qcom_spi_ecc_init_ctx_pipelined()
274 snandc->qspi->mtd = mtd; in qcom_spi_ecc_init_ctx_pipelined()
276 ecc_cfg->ecc_bytes_hw = 7; in qcom_spi_ecc_init_ctx_pipelined()
277 ecc_cfg->spare_bytes = 4; in qcom_spi_ecc_init_ctx_pipelined()
278 ecc_cfg->bbm_size = 1; in qcom_spi_ecc_init_ctx_pipelined()
279 ecc_cfg->bch_enabled = true; in qcom_spi_ecc_init_ctx_pipelined()
280 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; in qcom_spi_ecc_init_ctx_pipelined()
282 ecc_cfg->steps = 4; in qcom_spi_ecc_init_ctx_pipelined()
283 ecc_cfg->strength = 4; in qcom_spi_ecc_init_ctx_pipelined()
284 ecc_cfg->step_size = 512; in qcom_spi_ecc_init_ctx_pipelined()
285 ecc_cfg->cw_data = 516; in qcom_spi_ecc_init_ctx_pipelined()
286 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; in qcom_spi_ecc_init_ctx_pipelined()
287 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1; in qcom_spi_ecc_init_ctx_pipelined()
291 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_spi_ecc_init_ctx_pipelined()
292 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | in qcom_spi_ecc_init_ctx_pipelined()
295 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | in qcom_spi_ecc_init_ctx_pipelined()
298 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); in qcom_spi_ecc_init_ctx_pipelined()
300 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | in qcom_spi_ecc_init_ctx_pipelined()
306 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); in qcom_spi_ecc_init_ctx_pipelined()
308 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | in qcom_spi_ecc_init_ctx_pipelined()
310 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | in qcom_spi_ecc_init_ctx_pipelined()
313 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | in qcom_spi_ecc_init_ctx_pipelined()
321 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) | in qcom_spi_ecc_init_ctx_pipelined()
323 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | in qcom_spi_ecc_init_ctx_pipelined()
326 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); in qcom_spi_ecc_init_ctx_pipelined()
328 ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS; in qcom_spi_ecc_init_ctx_pipelined()
329 ecc_cfg->clrflashstatus = FS_READY_BSY_N; in qcom_spi_ecc_init_ctx_pipelined()
330 ecc_cfg->clrreadstatus = 0xc0; in qcom_spi_ecc_init_ctx_pipelined()
332 conf->step_size = ecc_cfg->step_size; in qcom_spi_ecc_init_ctx_pipelined()
333 conf->strength = ecc_cfg->strength; in qcom_spi_ecc_init_ctx_pipelined()
335 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); in qcom_spi_ecc_init_ctx_pipelined()
336 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); in qcom_spi_ecc_init_ctx_pipelined()
338 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", in qcom_spi_ecc_init_ctx_pipelined()
339 ecc_cfg->strength, ecc_cfg->step_size); in qcom_spi_ecc_init_ctx_pipelined()
344 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) in qcom_spi_ecc_cleanup_ctx_pipelined() argument
346 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); in qcom_spi_ecc_cleanup_ctx_pipelined()
351 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, in qcom_spi_ecc_prepare_io_req_pipelined() argument
354 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_prepare_io_req_pipelined()
355 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); in qcom_spi_ecc_prepare_io_req_pipelined()
357 snandc->qspi->ecc = ecc_cfg; in qcom_spi_ecc_prepare_io_req_pipelined()
358 snandc->qspi->raw_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
359 snandc->qspi->oob_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
360 snandc->qspi->page_rw = false; in qcom_spi_ecc_prepare_io_req_pipelined()
362 if (req->datalen) in qcom_spi_ecc_prepare_io_req_pipelined()
363 snandc->qspi->page_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
365 if (req->ooblen) in qcom_spi_ecc_prepare_io_req_pipelined()
366 snandc->qspi->oob_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
368 if (req->mode == MTD_OPS_RAW) in qcom_spi_ecc_prepare_io_req_pipelined()
369 snandc->qspi->raw_rw = true; in qcom_spi_ecc_prepare_io_req_pipelined()
374 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, in qcom_spi_ecc_finish_io_req_pipelined() argument
377 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); in qcom_spi_ecc_finish_io_req_pipelined()
378 struct mtd_info *mtd = nanddev_to_mtd(nand); in qcom_spi_ecc_finish_io_req_pipelined()
380 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ) in qcom_spi_ecc_finish_io_req_pipelined()
383 if (snandc->qspi->ecc_stats.failed) in qcom_spi_ecc_finish_io_req_pipelined()
384 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed; in qcom_spi_ecc_finish_io_req_pipelined()
386 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected; in qcom_spi_ecc_finish_io_req_pipelined()
388 if (snandc->qspi->ecc_stats.failed) in qcom_spi_ecc_finish_io_req_pipelined()
389 return -EBADMSG; in qcom_spi_ecc_finish_io_req_pipelined()
391 return snandc->qspi->ecc_stats.bitflips; in qcom_spi_ecc_finish_io_req_pipelined()
406 int num_cw = snandc->qspi->num_cw; in qcom_spi_set_read_loc()
408 if (cw == (num_cw - 1)) in qcom_spi_set_read_loc()
413 if (cw == (num_cw - 1)) in qcom_spi_set_read_loc()
424 __le32 *reg = &snandc->regs->read_location0; in qcom_spi_config_cw_read()
425 int num_cw = snandc->qspi->num_cw; in qcom_spi_config_cw_read()
428 if (cw == (num_cw - 1)) { in qcom_spi_config_cw_read()
429 reg = &snandc->regs->read_location_last0; in qcom_spi_config_cw_read()
434 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_read()
435 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_read()
444 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_block_erase()
447 snandc->buf_count = 0; in qcom_spi_block_erase()
448 snandc->buf_start = 0; in qcom_spi_block_erase()
452 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_block_erase()
453 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_block_erase()
454 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_block_erase()
455 snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE)); in qcom_spi_block_erase()
456 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw); in qcom_spi_block_erase()
457 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_block_erase()
459 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
460 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
461 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_block_erase()
465 dev_err(snandc->dev, "failure to erase block\n"); in qcom_spi_block_erase()
475 __le32 *reg = &snandc->regs->read_location0; in qcom_spi_config_single_cw_page_read()
476 int num_cw = snandc->qspi->num_cw; in qcom_spi_config_single_cw_page_read()
478 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_config_single_cw_page_read()
479 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_config_single_cw_page_read()
480 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_config_single_cw_page_read()
482 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_config_single_cw_page_read()
486 if (cw == (num_cw - 1)) { in qcom_spi_config_single_cw_page_read()
487 reg = &snandc->regs->read_location_last0; in qcom_spi_config_single_cw_page_read()
490 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_single_cw_page_read()
491 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_single_cw_page_read()
499 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_last_cw()
500 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_read_last_cw()
504 u32 num_cw = snandc->qspi->num_cw; in qcom_spi_read_last_cw()
509 size = ecc_cfg->cw_size; in qcom_spi_read_last_cw()
510 col = ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_last_cw()
512 memset(snandc->data_buffer, 0xff, size); in qcom_spi_read_last_cw()
513 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_read_last_cw()
514 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_last_cw()
516 cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | in qcom_spi_read_last_cw()
518 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_read_last_cw()
521 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_last_cw()
522 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_last_cw()
523 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_last_cw()
524 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_last_cw()
525 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); in qcom_spi_read_last_cw()
526 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); in qcom_spi_read_last_cw()
527 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_last_cw()
529 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); in qcom_spi_read_last_cw()
531 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); in qcom_spi_read_last_cw()
533 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); in qcom_spi_read_last_cw()
537 dev_err(snandc->dev, "failed to read last cw\n"); in qcom_spi_read_last_cw()
542 u32 flash = le32_to_cpu(snandc->reg_read_buf[0]); in qcom_spi_read_last_cw()
545 return -EIO; in qcom_spi_read_last_cw()
547 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_last_cw()
549 if (snandc->data_buffer[bbpos] == 0xff) in qcom_spi_read_last_cw()
550 snandc->data_buffer[bbpos + 1] = 0xff; in qcom_spi_read_last_cw()
551 if (snandc->data_buffer[bbpos] != 0xff) in qcom_spi_read_last_cw()
552 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos]; in qcom_spi_read_last_cw()
554 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); in qcom_spi_read_last_cw()
562 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_check_error()
563 int i, num_cw = snandc->qspi->num_cw; in qcom_spi_check_error()
568 snandc->qspi->ecc_stats.failed = 0; in qcom_spi_check_error()
569 snandc->qspi->ecc_stats.corrected = 0; in qcom_spi_check_error()
572 buf = (struct snandc_read_status *)snandc->reg_read_buf; in qcom_spi_check_error()
578 if (i == (num_cw - 1)) { in qcom_spi_check_error()
579 data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_check_error()
582 data_len = ecc_cfg->cw_data; in qcom_spi_check_error()
586 flash = le32_to_cpu(buf->snandc_flash); in qcom_spi_check_error()
587 buffer = le32_to_cpu(buf->snandc_buffer); in qcom_spi_check_error()
588 erased_cw = le32_to_cpu(buf->snandc_erased_cw); in qcom_spi_check_error()
591 if (ecc_cfg->bch_enabled) in qcom_spi_check_error()
605 snandc->qspi->ecc_stats.corrected += stat; in qcom_spi_check_error()
612 oob_buf += oob_len + ecc_cfg->bytes; in qcom_spi_check_error()
616 return -EIO; in qcom_spi_check_error()
619 snandc->qspi->ecc_stats.bitflips = max_bitflips; in qcom_spi_check_error()
621 snandc->qspi->ecc_stats.failed++; in qcom_spi_check_error()
633 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]); in qcom_spi_check_raw_flash_errors()
636 return -EIO; in qcom_spi_check_raw_flash_errors()
645 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_cw_raw()
646 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_read_cw_raw()
650 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_cw_raw()
653 snandc->buf_count = 0; in qcom_spi_read_cw_raw()
654 snandc->buf_start = 0; in qcom_spi_read_cw_raw()
657 raw_cw = num_cw - 1; in qcom_spi_read_cw_raw()
659 cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | in qcom_spi_read_cw_raw()
661 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_read_cw_raw()
664 col = ecc_cfg->cw_size * cw; in qcom_spi_read_cw_raw()
666 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_read_cw_raw()
667 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_cw_raw()
668 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_cw_raw()
669 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_cw_raw()
670 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_cw_raw()
671 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_cw_raw()
672 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); in qcom_spi_read_cw_raw()
673 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); in qcom_spi_read_cw_raw()
674 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_cw_raw()
676 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); in qcom_spi_read_cw_raw()
678 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_cw_raw()
679 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_cw_raw()
680 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); in qcom_spi_read_cw_raw()
682 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_cw_raw()
684 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_cw_raw()
688 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_read_cw_raw()
689 oob_size1 = ecc_cfg->bbm_size; in qcom_spi_read_cw_raw()
691 if (cw == (num_cw - 1)) { in qcom_spi_read_cw_raw()
692 data_size2 = NANDC_STEP_SIZE - data_size1 - in qcom_spi_read_cw_raw()
693 ((num_cw - 1) * 4); in qcom_spi_read_cw_raw()
694 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_cw_raw()
695 ecc_cfg->spare_bytes; in qcom_spi_read_cw_raw()
697 data_size2 = ecc_cfg->cw_data - data_size1; in qcom_spi_read_cw_raw()
698 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_cw_raw()
727 dev_err(snandc->dev, "failure to read raw cw %d\n", cw); in qcom_spi_read_cw_raw()
737 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_raw()
740 u32 num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_raw()
742 if (snandc->qspi->page_rw) in qcom_spi_read_page_raw()
743 data_buf = op->data.buf.in; in qcom_spi_read_page_raw()
745 oob_buf = snandc->qspi->oob_buf; in qcom_spi_read_page_raw()
754 data_buf += ecc_cfg->cw_data; in qcom_spi_read_page_raw()
756 oob_buf += ecc_cfg->bytes; in qcom_spi_read_page_raw()
765 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_ecc()
768 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_ecc()
770 data_buf = op->data.buf.in; in qcom_spi_read_page_ecc()
773 oob_buf = snandc->qspi->oob_buf; in qcom_spi_read_page_ecc()
776 snandc->buf_count = 0; in qcom_spi_read_page_ecc()
777 snandc->buf_start = 0; in qcom_spi_read_page_ecc()
780 cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | in qcom_spi_read_page_ecc()
781 (num_cw - 1) << CW_PER_PAGE; in qcom_spi_read_page_ecc()
782 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_ecc()
783 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_read_page_ecc()
785 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_read_page_ecc()
786 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_page_ecc()
787 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_page_ecc()
788 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_page_ecc()
789 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_ecc()
790 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_page_ecc()
791 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); in qcom_spi_read_page_ecc()
792 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); in qcom_spi_read_page_ecc()
793 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_page_ecc()
795 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); in qcom_spi_read_page_ecc()
799 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_page_ecc()
800 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_page_ecc()
801 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_page_ecc()
803 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_page_ecc()
810 if (i == (num_cw - 1)) { in qcom_spi_read_page_ecc()
811 data_size = 512 - ((num_cw - 1) << 2); in qcom_spi_read_page_ecc()
812 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_page_ecc()
813 ecc_cfg->spare_bytes; in qcom_spi_read_page_ecc()
815 data_size = ecc_cfg->cw_data; in qcom_spi_read_page_ecc()
816 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_ecc()
836 for (j = 0; j < ecc_cfg->bbm_size; j++) in qcom_spi_read_page_ecc()
851 dev_err(snandc->dev, "failure to read page\n"); in qcom_spi_read_page_ecc()
861 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_read_page_oob()
864 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; in qcom_spi_read_page_oob()
866 oob_buf = op->data.buf.in; in qcom_spi_read_page_oob()
871 snandc->buf_count = 0; in qcom_spi_read_page_oob()
872 snandc->buf_start = 0; in qcom_spi_read_page_oob()
876 cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | in qcom_spi_read_page_oob()
877 (num_cw - 1) << CW_PER_PAGE; in qcom_spi_read_page_oob()
878 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_oob()
879 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_read_page_oob()
881 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_read_page_oob()
882 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_read_page_oob()
883 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_read_page_oob()
884 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_read_page_oob()
885 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_oob()
886 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_read_page_oob()
887 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); in qcom_spi_read_page_oob()
888 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); in qcom_spi_read_page_oob()
889 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_read_page_oob()
891 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); in qcom_spi_read_page_oob()
893 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_read_page_oob()
894 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_read_page_oob()
895 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, in qcom_spi_read_page_oob()
897 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, in qcom_spi_read_page_oob()
904 if (i == (num_cw - 1)) { in qcom_spi_read_page_oob()
905 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_read_page_oob()
906 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_read_page_oob()
907 ecc_cfg->spare_bytes; in qcom_spi_read_page_oob()
909 data_size = ecc_cfg->cw_data; in qcom_spi_read_page_oob()
910 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_read_page_oob()
920 for (j = 0; j < ecc_cfg->bbm_size; j++) in qcom_spi_read_page_oob()
933 dev_err(snandc->dev, "failure to read oob\n"); in qcom_spi_read_page_oob()
943 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) in qcom_spi_read_page()
946 if (snandc->qspi->page_rw) in qcom_spi_read_page()
949 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) in qcom_spi_read_page()
952 if (snandc->qspi->oob_rw) in qcom_spi_read_page()
960 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); in qcom_spi_config_page_write()
961 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); in qcom_spi_config_page_write()
962 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, in qcom_spi_config_page_write()
968 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_write()
969 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_config_cw_write()
972 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); in qcom_spi_config_cw_write()
973 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1, in qcom_spi_config_cw_write()
980 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_raw()
981 struct mtd_info *mtd = snandc->qspi->mtd; in qcom_spi_program_raw()
984 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_raw()
987 cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | in qcom_spi_program_raw()
988 (num_cw - 1) << CW_PER_PAGE; in qcom_spi_program_raw()
989 cfg1 = ecc_cfg->cfg1_raw; in qcom_spi_program_raw()
992 data_buf = snandc->qspi->data_buf; in qcom_spi_program_raw()
994 oob_buf = snandc->qspi->oob_buf; in qcom_spi_program_raw()
997 snandc->buf_count = 0; in qcom_spi_program_raw()
998 snandc->buf_start = 0; in qcom_spi_program_raw()
1002 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_program_raw()
1003 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_raw()
1004 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_raw()
1005 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_raw()
1006 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_raw()
1007 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_raw()
1008 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); in qcom_spi_program_raw()
1009 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); in qcom_spi_program_raw()
1010 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_raw()
1018 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_program_raw()
1019 oob_size1 = ecc_cfg->bbm_size; in qcom_spi_program_raw()
1021 if (i == (num_cw - 1)) { in qcom_spi_program_raw()
1022 data_size2 = NANDC_STEP_SIZE - data_size1 - in qcom_spi_program_raw()
1023 ((num_cw - 1) << 2); in qcom_spi_program_raw()
1024 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_program_raw()
1025 ecc_cfg->spare_bytes; in qcom_spi_program_raw()
1027 data_size2 = ecc_cfg->cw_data - data_size1; in qcom_spi_program_raw()
1028 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; in qcom_spi_program_raw()
1054 dev_err(snandc->dev, "failure to write raw page\n"); in qcom_spi_program_raw()
1064 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_ecc()
1067 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_ecc()
1070 cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | in qcom_spi_program_ecc()
1071 (num_cw - 1) << CW_PER_PAGE; in qcom_spi_program_ecc()
1072 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_ecc()
1073 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_program_ecc()
1074 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; in qcom_spi_program_ecc()
1076 if (snandc->qspi->data_buf) in qcom_spi_program_ecc()
1077 data_buf = snandc->qspi->data_buf; in qcom_spi_program_ecc()
1079 oob_buf = snandc->qspi->oob_buf; in qcom_spi_program_ecc()
1081 snandc->buf_count = 0; in qcom_spi_program_ecc()
1082 snandc->buf_start = 0; in qcom_spi_program_ecc()
1086 snandc->regs->addr0 = snandc->qspi->addr1; in qcom_spi_program_ecc()
1087 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_ecc()
1088 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_ecc()
1089 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_ecc()
1090 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_ecc()
1091 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_ecc()
1092 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); in qcom_spi_program_ecc()
1093 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_ecc()
1100 if (i == (num_cw - 1)) { in qcom_spi_program_ecc()
1101 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_program_ecc()
1102 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + in qcom_spi_program_ecc()
1103 ecc_cfg->spare_bytes; in qcom_spi_program_ecc()
1105 data_size = ecc_cfg->cw_data; in qcom_spi_program_ecc()
1106 oob_size = ecc_cfg->bytes; in qcom_spi_program_ecc()
1111 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0); in qcom_spi_program_ecc()
1113 if (i == (num_cw - 1)) { in qcom_spi_program_ecc()
1115 oob_buf += ecc_cfg->bbm_size; in qcom_spi_program_ecc()
1131 dev_err(snandc->dev, "failure to write page\n"); in qcom_spi_program_ecc()
1141 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; in qcom_spi_program_oob()
1144 int num_cw = snandc->qspi->num_cw; in qcom_spi_program_oob()
1147 cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | in qcom_spi_program_oob()
1148 (num_cw - 1) << CW_PER_PAGE; in qcom_spi_program_oob()
1149 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_oob()
1150 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; in qcom_spi_program_oob()
1151 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; in qcom_spi_program_oob()
1153 col = ecc_cfg->cw_size * (num_cw - 1); in qcom_spi_program_oob()
1155 oob_buf = snandc->qspi->data_buf; in qcom_spi_program_oob()
1157 snandc->buf_count = 0; in qcom_spi_program_oob()
1158 snandc->buf_start = 0; in qcom_spi_program_oob()
1161 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); in qcom_spi_program_oob()
1162 snandc->regs->addr1 = snandc->qspi->addr2; in qcom_spi_program_oob()
1163 snandc->regs->cmd = snandc->qspi->cmd; in qcom_spi_program_oob()
1164 snandc->regs->cfg0 = cpu_to_le32(cfg0); in qcom_spi_program_oob()
1165 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_oob()
1166 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); in qcom_spi_program_oob()
1167 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); in qcom_spi_program_oob()
1168 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_program_oob()
1171 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); in qcom_spi_program_oob()
1172 oob_size = snandc->qspi->mtd->oobavail; in qcom_spi_program_oob()
1174 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); in qcom_spi_program_oob()
1176 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size, in qcom_spi_program_oob()
1177 oob_buf, 0, snandc->qspi->mtd->oobavail); in qcom_spi_program_oob()
1179 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0); in qcom_spi_program_oob()
1184 dev_err(snandc->dev, "failure to write oob\n"); in qcom_spi_program_oob()
1194 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) in qcom_spi_program_execute()
1197 if (snandc->qspi->page_rw) in qcom_spi_program_execute()
1200 if (snandc->qspi->oob_rw) in qcom_spi_program_execute()
1223 if (snandc->qspi->raw_rw) { in qcom_spi_cmd_mapping()
1247 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); in qcom_spi_cmd_mapping()
1248 return -EOPNOTSUPP; in qcom_spi_cmd_mapping()
1260 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); in qcom_spi_write_page()
1264 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) in qcom_spi_write_page()
1265 snandc->qspi->data_buf = (u8 *)op->data.buf.out; in qcom_spi_write_page()
1277 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); in qcom_spi_send_cmdaddr()
1282 s_op.addr1_reg = op->addr.val; in qcom_spi_send_cmdaddr()
1285 opcode = op->cmd.opcode; in qcom_spi_send_cmdaddr()
1291 s_op.addr1_reg = op->addr.val << 16; in qcom_spi_send_cmdaddr()
1292 s_op.addr2_reg = op->addr.val >> 16 & 0xff; in qcom_spi_send_cmdaddr()
1293 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); in qcom_spi_send_cmdaddr()
1294 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); in qcom_spi_send_cmdaddr()
1295 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1298 s_op.addr1_reg = (op->addr.val << 16); in qcom_spi_send_cmdaddr()
1299 s_op.addr2_reg = op->addr.val >> 16 & 0xff; in qcom_spi_send_cmdaddr()
1300 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); in qcom_spi_send_cmdaddr()
1301 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); in qcom_spi_send_cmdaddr()
1302 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1305 s_op.addr2_reg = (op->addr.val >> 16) & 0xffff; in qcom_spi_send_cmdaddr()
1306 s_op.addr1_reg = op->addr.val; in qcom_spi_send_cmdaddr()
1307 snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16); in qcom_spi_send_cmdaddr()
1308 snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); in qcom_spi_send_cmdaddr()
1309 snandc->qspi->cmd = cpu_to_le32(cmd); in qcom_spi_send_cmdaddr()
1315 snandc->buf_count = 0; in qcom_spi_send_cmdaddr()
1316 snandc->buf_start = 0; in qcom_spi_send_cmdaddr()
1320 snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg); in qcom_spi_send_cmdaddr()
1321 snandc->regs->exec = cpu_to_le32(1); in qcom_spi_send_cmdaddr()
1322 snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg); in qcom_spi_send_cmdaddr()
1323 snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg); in qcom_spi_send_cmdaddr()
1325 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in qcom_spi_send_cmdaddr()
1326 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_spi_send_cmdaddr()
1330 dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); in qcom_spi_send_cmdaddr()
1344 snandc->buf_count = 0; in qcom_spi_io_op()
1345 snandc->buf_start = 0; in qcom_spi_io_op()
1348 opcode = op->cmd.opcode; in qcom_spi_io_op()
1352 snandc->buf_count = 4; in qcom_spi_io_op()
1357 snandc->buf_count = 4; in qcom_spi_io_op()
1362 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out); in qcom_spi_io_op()
1363 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, in qcom_spi_io_op()
1373 return -EOPNOTSUPP; in qcom_spi_io_op()
1378 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode); in qcom_spi_io_op()
1382 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); in qcom_spi_io_op()
1387 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); in qcom_spi_io_op()
1389 memcpy(op->data.buf.in, &val, snandc->buf_count); in qcom_spi_io_op()
1397 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4) in qcom_spi_is_page_op()
1400 if (op->data.dir == SPI_MEM_DATA_IN) { in qcom_spi_is_page_op()
1401 if (op->addr.buswidth == 4 && op->data.buswidth == 4) in qcom_spi_is_page_op()
1404 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) in qcom_spi_is_page_op()
1407 } else if (op->data.dir == SPI_MEM_DATA_OUT) { in qcom_spi_is_page_op()
1408 if (op->data.buswidth == 4) in qcom_spi_is_page_op()
1410 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) in qcom_spi_is_page_op()
1422 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) in qcom_spi_supports_op()
1428 return ((!op->addr.nbytes || op->addr.buswidth == 1) && in qcom_spi_supports_op()
1429 (!op->dummy.nbytes || op->dummy.buswidth == 1) && in qcom_spi_supports_op()
1430 (!op->data.nbytes || op->data.buswidth == 1)); in qcom_spi_supports_op()
1435 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller); in qcom_spi_exec_op()
1437 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, in qcom_spi_exec_op()
1438 op->addr.val, op->addr.buswidth, op->addr.nbytes, in qcom_spi_exec_op()
1439 op->data.buswidth, op->data.nbytes); in qcom_spi_exec_op()
1442 if (op->data.dir == SPI_MEM_DATA_IN) in qcom_spi_exec_op()
1444 if (op->data.dir == SPI_MEM_DATA_OUT) in qcom_spi_exec_op()
1464 struct device *dev = &pdev->dev; in qcom_spi_probe()
1475 return -ENOMEM; in qcom_spi_probe()
1479 return -ENOMEM; in qcom_spi_probe()
1483 return -ENOMEM; in qcom_spi_probe()
1488 qspi->snandc = snandc; in qcom_spi_probe()
1490 snandc->dev = dev; in qcom_spi_probe()
1491 snandc->qspi = qspi; in qcom_spi_probe()
1492 snandc->qspi->ctlr = ctlr; in qcom_spi_probe()
1493 snandc->qspi->ecc = ecc; in qcom_spi_probe()
1497 dev_err(&pdev->dev, "failed to get device data\n"); in qcom_spi_probe()
1498 return -ENODEV; in qcom_spi_probe()
1501 snandc->props = dev_data; in qcom_spi_probe()
1502 snandc->dev = &pdev->dev; in qcom_spi_probe()
1504 snandc->core_clk = devm_clk_get(dev, "core"); in qcom_spi_probe()
1505 if (IS_ERR(snandc->core_clk)) in qcom_spi_probe()
1506 return PTR_ERR(snandc->core_clk); in qcom_spi_probe()
1508 snandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_spi_probe()
1509 if (IS_ERR(snandc->aon_clk)) in qcom_spi_probe()
1510 return PTR_ERR(snandc->aon_clk); in qcom_spi_probe()
1512 snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom"); in qcom_spi_probe()
1513 if (IS_ERR(snandc->qspi->iomacro_clk)) in qcom_spi_probe()
1514 return PTR_ERR(snandc->qspi->iomacro_clk); in qcom_spi_probe()
1516 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in qcom_spi_probe()
1517 if (IS_ERR(snandc->base)) in qcom_spi_probe()
1518 return PTR_ERR(snandc->base); in qcom_spi_probe()
1520 snandc->base_phys = res->start; in qcom_spi_probe()
1521 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res), in qcom_spi_probe()
1523 if (dma_mapping_error(dev, snandc->base_dma)) in qcom_spi_probe()
1524 return -ENXIO; in qcom_spi_probe()
1526 ret = clk_prepare_enable(snandc->core_clk); in qcom_spi_probe()
1530 ret = clk_prepare_enable(snandc->aon_clk); in qcom_spi_probe()
1534 ret = clk_prepare_enable(snandc->qspi->iomacro_clk); in qcom_spi_probe()
1547 snandc->qspi->ecc_eng.dev = &pdev->dev; in qcom_spi_probe()
1548 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; in qcom_spi_probe()
1549 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined; in qcom_spi_probe()
1550 snandc->qspi->ecc_eng.priv = snandc; in qcom_spi_probe()
1552 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); in qcom_spi_probe()
1554 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); in qcom_spi_probe()
1558 ctlr->num_chipselect = QPIC_QSPI_NUM_CS; in qcom_spi_probe()
1559 ctlr->mem_ops = &qcom_spi_mem_ops; in qcom_spi_probe()
1560 ctlr->mem_caps = &qcom_spi_mem_caps; in qcom_spi_probe()
1561 ctlr->dev.of_node = pdev->dev.of_node; in qcom_spi_probe()
1562 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL | in qcom_spi_probe()
1567 dev_err(&pdev->dev, "spi_register_controller failed.\n"); in qcom_spi_probe()
1576 clk_disable_unprepare(snandc->qspi->iomacro_clk); in qcom_spi_probe()
1578 clk_disable_unprepare(snandc->aon_clk); in qcom_spi_probe()
1580 clk_disable_unprepare(snandc->core_clk); in qcom_spi_probe()
1582 dma_unmap_resource(dev, res->start, resource_size(res), in qcom_spi_probe()
1597 clk_disable_unprepare(snandc->aon_clk); in qcom_spi_remove()
1598 clk_disable_unprepare(snandc->core_clk); in qcom_spi_remove()
1599 clk_disable_unprepare(snandc->qspi->iomacro_clk); in qcom_spi_remove()
1601 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), in qcom_spi_remove()
1612 .compatible = "qcom,ipq9574-snand",
1629 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");