Lines Matching full:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
55 #include <soc/tegra/pmc.h>
62 #include <dt-bindings/soc/tegra-pmc.h>
198 /* for secure PMC */
270 struct tegra_pmc *pmc; member
358 void (*init)(struct tegra_pmc *pmc);
359 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
362 void (*set_wake_filters)(struct tegra_pmc *pmc);
365 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
392 * struct tegra_pmc - NVIDIA Tegra PMC
393 * @dev: pointer to PMC device structure
400 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
416 * @pctl_dev: pin controller exposed by the PMC
417 * @domain: IRQ domain provided by the PMC
474 static struct tegra_pmc *pmc = &(struct tegra_pmc) { variable
485 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_readl() argument
489 if (pmc->tz_only) { in tegra_pmc_readl()
493 if (pmc->dev) in tegra_pmc_readl()
494 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
504 return readl(pmc->base + offset); in tegra_pmc_readl()
507 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
512 if (pmc->tz_only) { in tegra_pmc_writel()
516 if (pmc->dev) in tegra_pmc_writel()
517 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
524 writel(value, pmc->base + offset); in tegra_pmc_writel()
528 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_scratch_readl() argument
530 if (pmc->tz_only) in tegra_pmc_scratch_readl()
531 return tegra_pmc_readl(pmc, offset); in tegra_pmc_scratch_readl()
533 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
536 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
539 if (pmc->tz_only) in tegra_pmc_scratch_writel()
540 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
542 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
552 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
553 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
555 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
558 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) in tegra_powergate_is_valid() argument
560 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
563 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) in tegra_powergate_is_available() argument
565 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
568 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) in tegra_powergate_lookup() argument
572 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
575 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
576 if (!tegra_powergate_is_valid(pmc, i)) in tegra_powergate_lookup()
579 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
586 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra20_powergate_set() argument
594 * As per TRM documentation, the toggle command will be dropped by PMC in tegra20_powergate_set()
599 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra20_powergate_set()
601 /* wait for PMC to execute the command */ in tegra20_powergate_set()
609 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) in tegra_powergate_toggle_ready() argument
611 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); in tegra_powergate_toggle_ready()
614 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra114_powergate_set() argument
620 /* wait while PMC power gating is contended */ in tegra114_powergate_set()
621 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
626 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra114_powergate_set()
628 /* wait for PMC to accept the command */ in tegra114_powergate_set()
629 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
634 /* wait for PMC to execute the command */ in tegra114_powergate_set()
645 * @pmc: power management controller
649 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra_powergate_set() argument
654 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
657 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
660 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
664 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
666 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
671 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, in __tegra_powergate_remove_clamping() argument
676 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
683 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
684 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
700 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); in __tegra_powergate_remove_clamping()
703 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
798 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
814 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
826 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
848 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
877 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
905 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
924 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
950 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_on()
953 return tegra_powergate_set(pmc, id, true); in tegra_powergate_power_on()
963 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_off()
966 return tegra_powergate_set(pmc, id, false); in tegra_powergate_power_off()
972 * @pmc: power management controller
975 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) in tegra_powergate_is_powered() argument
977 if (!tegra_powergate_is_valid(pmc, id)) in tegra_powergate_is_powered()
989 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_remove_clamping()
992 return __tegra_powergate_remove_clamping(pmc, id); in tegra_powergate_remove_clamping()
1010 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_sequence_power_up()
1027 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1031 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1043 * @pmc: power management controller
1049 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, in tegra_get_cpu_powergate_id() argument
1052 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1053 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1066 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_is_powered()
1070 return tegra_powergate_is_powered(pmc, id); in tegra_pmc_cpu_is_powered()
1081 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_power_on()
1085 return tegra_powergate_set(pmc, id, true); in tegra_pmc_cpu_power_on()
1096 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_remove_clamping()
1107 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1121 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1142 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart()
1144 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart()
1164 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); in tegra_pmc_power_off_handler()
1179 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1180 status = tegra_powergate_is_powered(pmc, i); in powergate_show()
1184 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1239 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1274 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_powergate_add() argument
1276 struct device *dev = pmc->dev; in tegra_powergate_add()
1285 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1296 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1302 pg->pmc = pmc; in tegra_powergate_add()
1304 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1356 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1366 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1383 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1384 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1385 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1398 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_core_pd_add() argument
1404 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1411 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1413 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1418 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1424 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1428 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1438 static int tegra_powergate_init(struct tegra_pmc *pmc, in tegra_powergate_init() argument
1451 err = tegra_pmc_core_pd_add(pmc, np); in tegra_powergate_init()
1462 err = tegra_powergate_add(pmc, child); in tegra_powergate_init()
1496 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1530 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_find() argument
1534 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1535 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1536 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1541 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, in tegra_io_pad_prepare() argument
1556 if (pmc->clk) { in tegra_io_pad_prepare()
1557 rate = pmc->rate; in tegra_io_pad_prepare()
1559 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1563 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); in tegra_io_pad_prepare()
1568 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1574 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, in tegra_io_pad_poll() argument
1582 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1592 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) in tegra_io_pad_unprepare() argument
1594 if (pmc->clk) in tegra_io_pad_unprepare()
1595 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); in tegra_io_pad_unprepare()
1611 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_enable()
1613 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1617 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1619 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_enable()
1621 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1625 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); in tegra_io_pad_power_enable()
1627 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1629 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1633 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_enable()
1636 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1654 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_disable()
1656 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1660 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1662 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_disable()
1664 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1668 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); in tegra_io_pad_power_disable()
1670 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); in tegra_io_pad_power_disable()
1672 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1676 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_disable()
1679 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1684 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_is_powered() argument
1690 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_is_powered()
1692 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1702 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1707 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_set_voltage() argument
1713 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_set_voltage()
1720 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1722 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1723 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1730 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1733 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1735 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1738 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1745 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1748 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1755 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_get_voltage() argument
1760 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_voltage()
1767 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1768 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1770 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1781 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1789 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1804 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1814 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1816 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); in tegra_pmc_enter_suspend_mode()
1818 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1820 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); in tegra_pmc_enter_suspend_mode()
1822 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1825 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1829 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_parse_dt() argument
1834 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1838 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1842 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1846 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1850 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1855 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1858 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1860 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1863 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1865 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1869 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1871 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1872 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1875 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1877 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1879 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1882 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1885 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1888 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1893 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1894 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1896 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1897 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1902 static int tegra_pmc_init(struct tegra_pmc *pmc) in tegra_pmc_init() argument
1904 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1905 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1906 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1909 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1910 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1913 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1914 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1917 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1918 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1922 if (pmc->soc->init) in tegra_pmc_init()
1923 pmc->soc->init(pmc); in tegra_pmc_init()
1928 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) in tegra_pmc_init_tsense_reset() argument
1932 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1936 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1939 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1968 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1970 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1974 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
1992 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
1994 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1996 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1998 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2006 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_groups_count() local
2008 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2014 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); in tegra_io_pad_pinctrl_get_group_name() local
2016 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2024 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_group_pins() local
2026 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2044 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_get() local
2049 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_get()
2055 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2063 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2083 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_set() local
2090 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_set()
2111 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2134 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) in tegra_pmc_pinctrl_init() argument
2138 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2141 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2142 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2143 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2145 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2146 pmc); in tegra_pmc_pinctrl_init()
2147 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2148 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2149 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2162 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2163 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2164 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2166 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2169 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2179 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2180 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2181 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2183 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2186 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2191 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) in tegra_pmc_reset_sysfs_init() argument
2193 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2196 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2204 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2230 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc() local
2231 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2251 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2255 /* simple hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2261 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2281 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2283 /* GPIO hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2291 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2305 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_wake() local
2313 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2314 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2316 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2317 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2319 /* enable PMC wake */ in tegra210_pmc_irq_set_wake()
2325 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2332 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2339 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_type() local
2351 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2372 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2377 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) in tegra186_pmc_set_wake_filters() argument
2382 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2384 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2385 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2390 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_wake() local
2398 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2401 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2408 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2411 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2418 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_type() local
2421 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2427 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2428 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2434 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2435 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2440 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2441 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2448 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2481 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) in tegra_pmc_irq_init() argument
2486 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2495 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2496 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2497 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2498 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2499 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2500 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2501 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2503 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2504 &tegra_pmc_irq_domain_ops, pmc); in tegra_pmc_irq_init()
2505 if (!pmc->domain) { in tegra_pmc_irq_init()
2506 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2516 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); in tegra_pmc_clk_notify_cb() local
2521 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2525 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2529 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2542 tegra_pmc_readl(pmc, offset); in pmc_clk_fence_udelay()
2543 /* pmc clk propagation delay 2 us */ in pmc_clk_fence_udelay()
2552 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2563 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2566 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2577 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2586 val = tegra_pmc_readl(pmc, offs); in pmc_clk_set_state()
2588 tegra_pmc_writel(pmc, val, offs); in pmc_clk_set_state()
2618 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, in tegra_pmc_clk_out_register() argument
2625 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2648 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2674 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, in tegra_pmc_clk_gate_register() argument
2681 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2698 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, in tegra_pmc_clock_register() argument
2706 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2707 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2713 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2717 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2727 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2730 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2732 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2734 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2741 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2750 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2751 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2752 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2758 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2764 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2769 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2777 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2788 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2810 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_readl() local
2812 *value = tegra_pmc_readl(pmc, offset); in tegra_pmc_regmap_readl()
2818 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_writel() local
2820 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_regmap_writel()
2836 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) in tegra_pmc_regmap_init() argument
2841 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2842 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2845 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2855 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2869 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2872 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2886 if (pmc->soc->has_single_mmio_aperture) { in tegra_pmc_probe()
2887 pmc->wake = base; in tegra_pmc_probe()
2888 pmc->aotag = base; in tegra_pmc_probe()
2889 pmc->scratch = base; in tegra_pmc_probe()
2891 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); in tegra_pmc_probe()
2892 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2893 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2895 pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag"); in tegra_pmc_probe()
2896 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2897 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2903 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2904 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2905 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2907 pmc->scratch = NULL; in tegra_pmc_probe()
2911 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2912 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2913 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2917 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2920 if (pmc->scratch) { in tegra_pmc_probe()
2942 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2960 if (pmc->clk) { in tegra_pmc_probe()
2961 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2962 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2963 &pmc->clk_nb); in tegra_pmc_probe()
2970 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2973 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2975 err = tegra_pmc_init(pmc); in tegra_pmc_probe()
2977 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); in tegra_pmc_probe()
2981 tegra_pmc_init_tsense_reset(pmc); in tegra_pmc_probe()
2983 tegra_pmc_reset_sysfs_init(pmc); in tegra_pmc_probe()
2985 err = tegra_pmc_pinctrl_init(pmc); in tegra_pmc_probe()
2989 err = tegra_pmc_regmap_init(pmc); in tegra_pmc_probe()
2993 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2997 err = tegra_pmc_irq_init(pmc); in tegra_pmc_probe()
3001 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3002 iounmap(pmc->base); in tegra_pmc_probe()
3003 pmc->base = base; in tegra_pmc_probe()
3004 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3006 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3007 platform_set_drvdata(pdev, pmc); in tegra_pmc_probe()
3011 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3012 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3031 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) in wke_32kwritel() argument
3033 writel(value, pmc->wake + offset); in wke_32kwritel()
3037 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) in wke_write_wake_level() argument
3042 value = readl(pmc->wake + offset); in wke_write_wake_level()
3048 writel(value, pmc->wake + offset); in wke_write_wake_level()
3051 static void wke_write_wake_levels(struct tegra_pmc *pmc) in wke_write_wake_levels() argument
3055 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3056 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3059 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) in wke_clear_sw_wake_status() argument
3061 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); in wke_clear_sw_wake_status()
3064 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) in wke_read_sw_wake_status() argument
3069 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3070 wke_write_wake_level(pmc, i, 0); in wke_read_sw_wake_status()
3072 wke_clear_sw_wake_status(pmc); in wke_read_sw_wake_status()
3074 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3082 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3083 wke_write_wake_level(pmc, i, 1); in wke_read_sw_wake_status()
3092 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3094 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3096 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3097 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3100 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3104 static void wke_clear_wake_status(struct tegra_pmc *pmc) in wke_clear_wake_status() argument
3110 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3111 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3112 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3115 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); in wke_clear_wake_status()
3120 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, in tegra186_pmc_process_wake_events() argument
3125 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3132 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3136 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3140 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3150 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3151 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3152 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3154 tegra186_pmc_process_wake_events(pmc, i, status); in tegra186_pmc_wake_syscore_resume()
3160 wke_read_sw_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3165 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3166 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3167 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3168 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3170 /* Clear PMC Wake Status registers while going to suspend */ in tegra186_pmc_wake_syscore_suspend()
3171 wke_clear_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3172 wke_write_wake_levels(pmc); in tegra186_pmc_wake_syscore_suspend()
3180 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_suspend() local
3182 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); in tegra_pmc_suspend()
3189 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_resume() local
3191 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
3219 static void tegra20_pmc_init(struct tegra_pmc *pmc) in tegra20_pmc_init() argument
3224 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3226 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3228 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3230 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3235 if (pmc->corereq_high) in tegra20_pmc_init()
3241 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3244 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3246 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3249 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3250 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3251 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3252 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3253 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
3255 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); in tegra20_pmc_init()
3259 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra20_pmc_setup_irq_polarity() argument
3265 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3272 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3825 static void tegra186_pmc_init(struct tegra_pmc *pmc) in tegra186_pmc_init() argument
3827 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3828 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3830 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3833 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra186_pmc_setup_irq_polarity() argument
3844 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3852 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
4251 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4252 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4253 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4254 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4255 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4256 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4257 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4258 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4259 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4272 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4280 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4283 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4286 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4288 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4296 .name = "tegra-pmc",
4308 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) in tegra_pmc_detect_tz_only() argument
4312 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4319 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4320 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4324 pr_info("access to PMC is restricted to TZ\n"); in tegra_pmc_detect_tz_only()
4329 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4346 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4353 * a PMC node. in tegra_pmc_early_init()
4356 * that didn't contain a PMC node. Note that in this case the in tegra_pmc_early_init()
4381 pr_err("failed to get PMC registers\n"); in tegra_pmc_early_init()
4387 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4388 if (!pmc->base) { in tegra_pmc_early_init()
4389 pr_err("failed to map PMC registers\n"); in tegra_pmc_early_init()
4395 pmc->soc = match->data; in tegra_pmc_early_init()
4397 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4398 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4401 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4402 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4403 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4406 * Invert the interrupt polarity if a PMC device tree node in tegra_pmc_early_init()
4411 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()