Lines Matching +full:crypto +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
32 /* BIST ("built-in self-test") status flags */
39 #define qcom_ice_writel(engine, val, reg) \ argument
40 writel((val), (engine)->base + (reg))
42 #define qcom_ice_readl(engine, reg) \ argument
43 readl((engine)->base + (reg))
55 struct device *dev = ice->dev; in qcom_ice_check_supported()
67 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
107 * Wait until the ICE BIST (built-in self-test) has completed.
113 * practice, (b) ICE is documented to reject crypto requests if the BIST
116 * and not relying on hardware-level self-tests.
123 err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, in qcom_ice_wait_bist_status()
127 dev_err(ice->dev, "Timed out waiting for ICE self-test to complete\n"); in qcom_ice_wait_bist_status()
143 struct device *dev = ice->dev; in qcom_ice_resume()
146 err = clk_prepare_enable(ice->core_clk); in qcom_ice_resume()
159 clk_disable_unprepare(ice->core_clk); in qcom_ice_suspend()
170 struct device *dev = ice->dev; in qcom_ice_program_key()
178 /* Only AES-256-XTS has been tested so far. */ in qcom_ice_program_key()
182 "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", in qcom_ice_program_key()
184 return -EINVAL; in qcom_ice_program_key()
212 struct qcom_ice *engine; in qcom_ice_create() local
215 return ERR_PTR(-EPROBE_DEFER); in qcom_ice_create()
222 engine = devm_kzalloc(dev, sizeof(*engine), GFP_KERNEL); in qcom_ice_create()
223 if (!engine) in qcom_ice_create()
224 return ERR_PTR(-ENOMEM); in qcom_ice_create()
226 engine->dev = dev; in qcom_ice_create()
227 engine->base = base; in qcom_ice_create()
236 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); in qcom_ice_create()
237 if (!engine->core_clk) in qcom_ice_create()
238 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); in qcom_ice_create()
239 if (!engine->core_clk) in qcom_ice_create()
240 engine->core_clk = devm_clk_get_enabled(dev, NULL); in qcom_ice_create()
241 if (IS_ERR(engine->core_clk)) in qcom_ice_create()
242 return ERR_CAST(engine->core_clk); in qcom_ice_create()
244 if (!qcom_ice_check_supported(engine)) in qcom_ice_create()
245 return ERR_PTR(-EOPNOTSUPP); in qcom_ice_create()
247 dev_dbg(dev, "Registered Qualcomm Inline Crypto Engine\n"); in qcom_ice_create()
249 return engine; in qcom_ice_create()
253 * of_qcom_ice_get() - get an ICE instance from a DT node
273 if (!dev || !dev->of_node) in of_qcom_ice_get()
274 return ERR_PTR(-ENODEV); in of_qcom_ice_get()
283 base = devm_ioremap_resource(&pdev->dev, res); in of_qcom_ice_get()
288 return qcom_ice_create(&pdev->dev, base); in of_qcom_ice_get()
296 struct device_node *node __free(device_node) = of_parse_phandle(dev->of_node, in of_qcom_ice_get()
303 dev_err(dev, "Cannot find device node %s\n", node->name); in of_qcom_ice_get()
304 return ERR_PTR(-EPROBE_DEFER); in of_qcom_ice_get()
310 dev_name(&pdev->dev)); in of_qcom_ice_get()
312 return ERR_PTR(-EPROBE_DEFER); in of_qcom_ice_get()
315 link = device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER); in of_qcom_ice_get()
317 dev_err(&pdev->dev, in of_qcom_ice_get()
321 ice = ERR_PTR(-EINVAL); in of_qcom_ice_get()
329 struct platform_device *pdev = to_platform_device(ice->dev); in qcom_ice_put()
341 * devm_of_qcom_ice_get() - Devres managed helper to get an ICE instance from
360 return ERR_PTR(-ENOMEM); in devm_of_qcom_ice_get()
376 struct qcom_ice *engine; in qcom_ice_probe() local
381 dev_warn(&pdev->dev, "ICE registers not found\n"); in qcom_ice_probe()
385 engine = qcom_ice_create(&pdev->dev, base); in qcom_ice_probe()
386 if (IS_ERR(engine)) in qcom_ice_probe()
387 return PTR_ERR(engine); in qcom_ice_probe()
389 platform_set_drvdata(pdev, engine); in qcom_ice_probe()
395 { .compatible = "qcom,inline-crypto-engine" },
403 .name = "qcom-ice",
410 MODULE_DESCRIPTION("Qualcomm Inline Crypto Engine driver");