Lines Matching +full:rk3066 +full:- +full:usb
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rk3036-power.h>
29 #include <dt-bindings/power/rk3066-power.h>
30 #include <dt-bindings/power/rk3128-power.h>
31 #include <dt-bindings/power/rk3188-power.h>
32 #include <dt-bindings/power/rk3228-power.h>
33 #include <dt-bindings/power/rk3288-power.h>
34 #include <dt-bindings/power/rk3328-power.h>
35 #include <dt-bindings/power/rk3366-power.h>
36 #include <dt-bindings/power/rk3368-power.h>
37 #include <dt-bindings/power/rk3399-power.h>
38 #include <dt-bindings/power/rk3568-power.h>
39 #include <dt-bindings/power/rockchip,rk3576-power.h>
40 #include <dt-bindings/power/rk3588-power.h>
211 * Dynamic Memory Controller may need to coordinate with us -- see
214 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
245 mutex_lock(&pmu->mutex); in rockchip_pmu_block()
249 * enabled for the duration of power-domain transitions. Most in rockchip_pmu_block()
251 * particular, DRAM DVFS / memory-controller idle) must be handled by in rockchip_pmu_block()
257 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_block()
258 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
261 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pmu_block()
263 dev_err(pmu->dev, in rockchip_pmu_block()
265 genpd->name, ret); in rockchip_pmu_block()
274 for (i = i - 1; i >= 0; i--) { in rockchip_pmu_block()
275 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
278 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_block()
281 mutex_unlock(&pmu->mutex); in rockchip_pmu_block()
298 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_unblock()
299 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_unblock()
302 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_unblock()
306 mutex_unlock(&pmu->mutex); in rockchip_pmu_unblock()
318 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
319 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
322 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
323 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
330 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
336 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_ungate_clk()
337 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_ungate_clk()
339 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; in rockchip_pmu_ungate_clk()
341 if (!pd_info->clk_ungate_mask) in rockchip_pmu_ungate_clk()
344 if (!pmu->info->clk_ungate_offset) in rockchip_pmu_ungate_clk()
347 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : in rockchip_pmu_ungate_clk()
349 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); in rockchip_pmu_ungate_clk()
357 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
358 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
359 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
360 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
366 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
368 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
369 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
370 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
371 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
373 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
374 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
379 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
381 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
384 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
386 genpd->name, val); in rockchip_pmu_set_idle_request()
393 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
395 genpd->name, is_idle); in rockchip_pmu_set_idle_request()
406 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
407 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
409 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
410 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
412 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
413 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
415 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
416 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
418 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
419 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
421 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
430 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
431 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
433 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
434 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
436 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
437 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
439 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
440 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
442 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
443 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
445 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
453 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
456 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
457 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
459 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
462 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
463 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
466 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
469 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
474 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
477 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
478 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
481 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
486 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
489 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
490 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
493 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
498 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
499 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
506 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
508 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
514 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
515 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
521 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
523 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
527 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
528 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
534 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
536 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
546 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
547 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
548 u32 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
553 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
556 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
559 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
560 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
561 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
562 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
564 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
565 pd->info->pwr_mask, on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
579 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n", in rockchip_do_pmu_set_power_domain()
580 genpd->name, on ? "on" : "off", is_on); in rockchip_do_pmu_set_power_domain()
587 pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
588 pd->info->pwr_mask, on, 0, 0, 0, &res); in rockchip_do_pmu_set_power_domain()
595 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
598 guard(mutex)(&pmu->mutex); in rockchip_pd_power()
603 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
605 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
635 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
642 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply); in rockchip_pd_regulator_disable()
647 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_regulator_enable()
649 if (!pd->info->need_regulator) in rockchip_pd_regulator_enable()
652 if (IS_ERR_OR_NULL(pd->supply)) { in rockchip_pd_regulator_enable()
653 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain"); in rockchip_pd_regulator_enable()
655 if (IS_ERR(pd->supply)) in rockchip_pd_regulator_enable()
656 return PTR_ERR(pd->supply); in rockchip_pd_regulator_enable()
659 return regulator_enable(pd->supply); in rockchip_pd_regulator_enable()
669 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret); in rockchip_pd_power_on()
700 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
709 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
726 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
743 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
746 return -EINVAL; in rockchip_pm_add_one_domain()
749 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
750 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
752 return -EINVAL; in rockchip_pm_add_one_domain()
755 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
758 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
760 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
762 return -EINVAL; in rockchip_pm_add_one_domain()
765 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
767 return -ENOMEM; in rockchip_pm_add_one_domain()
769 pd->info = pd_info; in rockchip_pm_add_one_domain()
770 pd->pmu = pmu; in rockchip_pm_add_one_domain()
771 pd->node = node; in rockchip_pm_add_one_domain()
773 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
774 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
775 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
776 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
777 if (!pd->clks) in rockchip_pm_add_one_domain()
778 return -ENOMEM; in rockchip_pm_add_one_domain()
780 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
781 node, pd->num_clks); in rockchip_pm_add_one_domain()
782 pd->num_clks = 0; in rockchip_pm_add_one_domain()
785 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
786 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
787 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
788 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
789 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
796 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
800 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", in rockchip_pm_add_one_domain()
803 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
804 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
805 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
807 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
808 error = -ENOMEM; in rockchip_pm_add_one_domain()
813 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, in rockchip_pm_add_one_domain()
814 pd->num_qos, in rockchip_pm_add_one_domain()
817 if (!pd->qos_save_regs[j]) { in rockchip_pm_add_one_domain()
818 error = -ENOMEM; in rockchip_pm_add_one_domain()
823 for (j = 0; j < pd->num_qos; j++) { in rockchip_pm_add_one_domain()
826 error = -ENODEV; in rockchip_pm_add_one_domain()
829 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); in rockchip_pm_add_one_domain()
831 if (IS_ERR(pd->qos_regmap[j])) { in rockchip_pm_add_one_domain()
832 error = -ENODEV; in rockchip_pm_add_one_domain()
838 if (pd->info->name) in rockchip_pm_add_one_domain()
839 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
841 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
842 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
843 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
844 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
845 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
846 pd->genpd.flags = GENPD_FLAG_PM_CLK; in rockchip_pm_add_one_domain()
847 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
848 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
849 pm_genpd_init(&pd->genpd, NULL, in rockchip_pm_add_one_domain()
851 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); in rockchip_pm_add_one_domain()
853 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
857 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
859 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
871 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
873 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
874 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
876 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
877 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
879 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
880 mutex_lock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
881 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
882 mutex_unlock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
893 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
894 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
909 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
911 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
925 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
930 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
934 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
941 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
946 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
950 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
951 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
954 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
955 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
966 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
967 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
975 return -ENODEV; in rockchip_pm_domain_probe()
981 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
984 return -ENOMEM; in rockchip_pm_domain_probe()
986 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
987 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
989 pmu->info = pmu_info; in rockchip_pm_domain_probe()
991 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
992 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
994 parent = dev->parent; in rockchip_pm_domain_probe()
997 return -ENODEV; in rockchip_pm_domain_probe()
1000 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
1001 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
1003 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
1010 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
1011 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
1012 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
1013 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
1014 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
1015 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
1017 error = -ENODEV; in rockchip_pm_domain_probe()
1046 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
1064 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
1082 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
1222 …[RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0…
1262 …[RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT…
1456 .compatible = "rockchip,px30-power-controller",
1460 .compatible = "rockchip,rk3036-power-controller",
1464 .compatible = "rockchip,rk3066-power-controller",
1468 .compatible = "rockchip,rk3128-power-controller",
1472 .compatible = "rockchip,rk3188-power-controller",
1476 .compatible = "rockchip,rk3228-power-controller",
1480 .compatible = "rockchip,rk3288-power-controller",
1484 .compatible = "rockchip,rk3328-power-controller",
1488 .compatible = "rockchip,rk3366-power-controller",
1492 .compatible = "rockchip,rk3368-power-controller",
1496 .compatible = "rockchip,rk3399-power-controller",
1500 .compatible = "rockchip,rk3568-power-controller",
1504 .compatible = "rockchip,rk3576-power-controller",
1508 .compatible = "rockchip,rk3588-power-controller",
1512 .compatible = "rockchip,rv1126-power-controller",
1521 .name = "rockchip-pm-domain",