Lines Matching full:bit
14 {"PMC_0", BIT(0)},
15 {"FUSE_OSSE", BIT(1)},
16 {"ESPISPI", BIT(2)},
17 {"XHCI", BIT(3)},
18 {"SPA", BIT(4)},
19 {"SPB", BIT(5)},
20 {"MPFPW2", BIT(6)},
21 {"GBE", BIT(7)},
23 {"SBR16B20", BIT(0)},
24 {"SBR8B20", BIT(1)},
25 {"SBR16B21", BIT(2)},
26 {"DBG_SBR16B", BIT(3)},
27 {"OSSE_HOTHAM", BIT(4)},
28 {"D2D_DISP_1", BIT(5)},
29 {"LPSS", BIT(6)},
30 {"LPC", BIT(7)},
32 {"SMB", BIT(0)},
33 {"ISH", BIT(1)},
34 {"SBR16B2", BIT(2)},
35 {"NPK_0", BIT(3)},
36 {"D2D_NOC_1", BIT(4)},
37 {"SBR8B2", BIT(5)},
38 {"FUSE", BIT(6)},
39 {"SBR16B0", BIT(7)},
41 {"PSF0", BIT(0)},
42 {"XDCI", BIT(1)},
43 {"EXI", BIT(2)},
44 {"CSE", BIT(3)},
45 {"KVMCC", BIT(4)},
46 {"PMT", BIT(5)},
47 {"CLINK", BIT(6)},
48 {"PTIO", BIT(7)},
50 {"USBR0", BIT(0)},
51 {"SUSRAM", BIT(1)},
52 {"SMT1", BIT(2)},
53 {"MPFPW1", BIT(3)},
54 {"SMS2", BIT(4)},
55 {"SMS1", BIT(5)},
56 {"CSMERTC", BIT(6)},
57 {"CSMEPSF", BIT(7)},
59 {"D2D_NOC_0", BIT(0)},
60 {"ESE", BIT(1)},
61 {"P2SB8B", BIT(2)},
62 {"SBR16B7", BIT(3)},
63 {"SBR16B3", BIT(4)},
64 {"OSSE_SMT1", BIT(5)},
65 {"D2D_DISP", BIT(6)},
66 {"DBG_SBR", BIT(7)},
68 {"U3FPW1", BIT(0)},
69 {"FIA_X", BIT(1)},
70 {"PSF4", BIT(2)},
71 {"CNVI", BIT(3)},
72 {"UFSX2", BIT(4)},
73 {"ENDBG", BIT(5)},
74 {"DBC", BIT(6)},
75 {"FIA_PG", BIT(7)},
77 {"D2D_IPU", BIT(0)},
78 {"NPK1", BIT(1)},
79 {"FIACPCB_X", BIT(2)},
80 {"SBR8B4", BIT(3)},
81 {"DBG_PSF", BIT(4)},
82 {"PSF6", BIT(5)},
83 {"UFSPW1", BIT(6)},
84 {"FIA_U", BIT(7)},
86 {"PSF8", BIT(0)},
87 {"SBR16B4", BIT(1)},
88 {"SBR16B5", BIT(2)},
89 {"FIACPCB_U", BIT(3)},
90 {"TAM", BIT(4)},
91 {"D2D_NOC_2", BIT(5)},
92 {"TBTLSX", BIT(6)},
93 {"THC0", BIT(7)},
95 {"THC1", BIT(0)},
96 {"PMC_1", BIT(1)},
97 {"SBR8B1", BIT(2)},
98 {"TCSS", BIT(3)},
99 {"DISP_PGA", BIT(4)},
100 {"SBR16B1", BIT(5)},
101 {"SBRG", BIT(6)},
102 {"PSF5", BIT(7)},
104 {"P2SB16B", BIT(0)},
105 {"ACE_0", BIT(1)},
106 {"ACE_1", BIT(2)},
107 {"ACE_2", BIT(3)},
108 {"ACE_3", BIT(4)},
109 {"ACE_4", BIT(5)},
110 {"ACE_5", BIT(6)},
111 {"ACE_6", BIT(7)},
113 {"ACE_7", BIT(0)},
114 {"ACE_8", BIT(1)},
115 {"ACE_9", BIT(2)},
116 {"ACE_10", BIT(3)},
117 {"FIACPCB_PG", BIT(4)},
118 {"SBR16B6", BIT(5)},
119 {"OSSE", BIT(6)},
120 {"SBR8B0", BIT(7)},
166 {"AON2_OFF_STS", BIT(0), 1},
167 {"AON3_OFF_STS", BIT(1), 0},
168 {"AON4_OFF_STS", BIT(2), 1},
169 {"AON5_OFF_STS", BIT(3), 1},
170 {"AON1_OFF_STS", BIT(4), 0},
171 {"XTAL_LVM_OFF_STS", BIT(5), 0},
172 {"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
173 {"USB3_PLL_OFF_STS", BIT(8), 1},
174 {"AON3_SPL_OFF_STS", BIT(9), 1},
175 {"MPFPW2_0_PLL_OFF_STS", BIT(12), 1},
176 {"XTAL_AGGR_OFF_STS", BIT(17), 1},
177 {"USB2_PLL_OFF_STS", BIT(18), 0},
178 {"SAF_PLL_OFF_STS", BIT(19), 1},
179 {"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
180 {"DDI_PLL_OFF_STS", BIT(21), 1},
181 {"FILTER_PLL_OFF_STS", BIT(22), 1},
182 {"ACE_PLL_OFF_STS", BIT(24), 0},
183 {"FABRIC_PLL_OFF_STS", BIT(25), 1},
184 {"SOC_PLL_OFF_STS", BIT(26), 1},
185 {"REF_PLL_OFF_STS", BIT(28), 1},
186 {"IMG_PLL_OFF_STS", BIT(29), 1},
187 {"RTC_PLL_OFF_STS", BIT(31), 0},
192 {"PMC_PGD0_PG_STS", BIT(0), 0},
193 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
194 {"ESPISPI_PGD0_PG_STS", BIT(2), 0},
195 {"XHCI_PGD0_PG_STS", BIT(3), 1},
196 {"SPA_PGD0_PG_STS", BIT(4), 1},
197 {"SPB_PGD0_PG_STS", BIT(5), 1},
198 {"MPFPW2_PGD0_PG_STS", BIT(6), 0},
199 {"GBE_PGD0_PG_STS", BIT(7), 1},
200 {"SBR16B20_PGD0_PG_STS", BIT(8), 0},
201 {"SBR8B20_PGD0_PG_STS", BIT(9), 0},
202 {"SBR16B21_PGD0_PG_STS", BIT(10), 0},
203 {"DBG_PGD0_PG_STS", BIT(11), 0},
204 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(12), 1},
205 {"D2D_DISP_PGD1_PG_STS", BIT(13), 1},
206 {"LPSS_PGD0_PG_STS", BIT(14), 1},
207 {"LPC_PGD0_PG_STS", BIT(15), 0},
208 {"SMB_PGD0_PG_STS", BIT(16), 0},
209 {"ISH_PGD0_PG_STS", BIT(17), 0},
210 {"SBR16B2_PGD0_PG_STS", BIT(18), 0},
211 {"NPK_PGD0_PG_STS", BIT(19), 0},
212 {"D2D_NOC_PGD1_PG_STS", BIT(20), 1},
213 {"SBR8B2_PGD0_PG_STS", BIT(21), 0},
214 {"FUSE_PGD0_PG_STS", BIT(22), 0},
215 {"SBR16B0_PGD0_PG_STS", BIT(23), 0},
216 {"PSF0_PGD0_PG_STS", BIT(24), 0},
217 {"XDCI_PGD0_PG_STS", BIT(25), 1},
218 {"EXI_PGD0_PG_STS", BIT(26), 0},
219 {"CSE_PGD0_PG_STS", BIT(27), 1},
220 {"KVMCC_PGD0_PG_STS", BIT(28), 1},
221 {"PMT_PGD0_PG_STS", BIT(29), 1},
222 {"CLINK_PGD0_PG_STS", BIT(30), 1},
223 {"PTIO_PGD0_PG_STS", BIT(31), 1},
228 {"USBR0_PGD0_PG_STS", BIT(0), 1},
229 {"SUSRAM_PGD0_PG_STS", BIT(1), 1},
230 {"SMT1_PGD0_PG_STS", BIT(2), 1},
231 {"MPFPW1_PGD0_PG_STS", BIT(3), 0},
232 {"SMS2_PGD0_PG_STS", BIT(4), 1},
233 {"SMS1_PGD0_PG_STS", BIT(5), 1},
234 {"CSMERTC_PGD0_PG_STS", BIT(6), 0},
235 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
236 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0},
237 {"ESE_PGD0_PG_STS", BIT(9), 1},
238 {"P2SB8B_PGD0_PG_STS", BIT(10), 1},
239 {"SBR16B7_PGD0_PG_STS", BIT(11), 0},
240 {"SBR16B3_PGD0_PG_STS", BIT(12), 0},
241 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
242 {"D2D_DISP_PGD0_PG_STS", BIT(14), 1},
243 {"DBG_SBR_PGD0_PG_STS", BIT(15), 0},
244 {"U3FPW1_PGD0_PG_STS", BIT(16), 0},
245 {"FIA_X_PGD0_PG_STS", BIT(17), 0},
246 {"PSF4_PGD0_PG_STS", BIT(18), 0},
247 {"CNVI_PGD0_PG_STS", BIT(19), 0},
248 {"UFSX2_PGD0_PG_STS", BIT(20), 1},
249 {"ENDBG_PGD0_PG_STS", BIT(21), 0},
250 {"DBC_PGD0_PG_STS", BIT(22), 0},
251 {"FIA_PG_PGD0_PG_STS", BIT(23), 0},
252 {"D2D_IPU_PGD0_PG_STS", BIT(24), 1},
253 {"NPK_PGD1_PG_STS", BIT(25), 0},
254 {"FIACPCB_X_PGD0_PG_STS", BIT(26), 0},
255 {"SBR8B4_PGD0_PG_STS", BIT(27), 0},
256 {"DBG_PSF_PGD0_PG_STS", BIT(28), 0},
257 {"PSF6_PGD0_PG_STS", BIT(29), 0},
258 {"UFSPW1_PGD0_PG_STS", BIT(30), 0},
259 {"FIA_U_PGD0_PG_STS", BIT(31), 0},
264 {"PSF8_PGD0_PG_STS", BIT(0), 0},
265 {"SBR16B4_PGD0_PG_STS", BIT(1), 0},
266 {"SBR16B5_PGD0_PG_STS", BIT(2), 0},
267 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
268 {"TAM_PGD0_PG_STS", BIT(4), 1},
269 {"D2D_NOC_PGD0_PG_STS", BIT(5), 1},
270 {"TBTLSX_PGD0_PG_STS", BIT(6), 1},
271 {"THC0_PGD0_PG_STS", BIT(7), 1},
272 {"THC1_PGD0_PG_STS", BIT(8), 1},
273 {"PMC_PGD1_PG_STS", BIT(9), 0},
274 {"SBR8B1_PGD0_PG_STS", BIT(10), 0},
275 {"TCSS_PGD0_PG_STS", BIT(11), 0},
276 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0},
277 {"SBR16B1_PGD0_PG_STS", BIT(13), 0},
278 {"SBRG_PGD0_PG_STS", BIT(14), 0},
279 {"PSF5_PGD0_PG_STS", BIT(15), 0},
280 {"P2SB16B_PGD0_PG_STS", BIT(16), 1},
281 {"ACE_PGD0_PG_STS", BIT(17), 0},
282 {"ACE_PGD1_PG_STS", BIT(18), 0},
283 {"ACE_PGD2_PG_STS", BIT(19), 0},
284 {"ACE_PGD3_PG_STS", BIT(20), 0},
285 {"ACE_PGD4_PG_STS", BIT(21), 0},
286 {"ACE_PGD5_PG_STS", BIT(22), 0},
287 {"ACE_PGD6_PG_STS", BIT(23), 0},
288 {"ACE_PGD7_PG_STS", BIT(24), 0},
289 {"ACE_PGD8_PG_STS", BIT(25), 0},
290 {"ACE_PGD9_PG_STS", BIT(26), 0},
291 {"ACE_PGD10_PG_STS", BIT(27), 0},
292 {"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0},
293 {"SBR16B6_PGD0_PG_STS", BIT(29), 0},
294 {"OSSE_PGD0_PG_STS", BIT(30), 1},
295 {"SBR8B0_PGD0_PG_STS", BIT(31), 0},
300 {"LPSS_D3_STS", BIT(3), 1},
301 {"XDCI_D3_STS", BIT(4), 1},
302 {"XHCI_D3_STS", BIT(5), 1},
303 {"OSSE_D3_STS", BIT(6), 0},
304 {"SPA_D3_STS", BIT(12), 0},
305 {"SPB_D3_STS", BIT(13), 0},
306 {"ESPISPI_D3_STS", BIT(18), 0},
307 {"PSTH_D3_STS", BIT(21), 0},
308 {"OSSE_SMT1_D3_STS", BIT(30), 0},
313 {"GBE_D3_STS", BIT(19), 0},
314 {"ITSS_D3_STS", BIT(23), 0},
315 {"CNVI_D3_STS", BIT(27), 0},
316 {"UFSX2_D3_STS", BIT(28), 1},
317 {"OSSE_HOTHAM_D3_STS", BIT(29), 0},
318 {"ESE_D3_STS", BIT(30), 0},
323 {"CSMERTC_D3_STS", BIT(1), 0},
324 {"SUSRAM_D3_STS", BIT(2), 0},
325 {"CSE_D3_STS", BIT(4), 0},
326 {"KVMCC_D3_STS", BIT(5), 0},
327 {"USBR0_D3_STS", BIT(6), 0},
328 {"ISH_D3_STS", BIT(7), 0},
329 {"SMT1_D3_STS", BIT(8), 0},
330 {"SMT2_D3_STS", BIT(9), 0},
331 {"SMT3_D3_STS", BIT(10), 0},
332 {"OSSE_SMT2_D3_STS", BIT(12), 0},
333 {"CLINK_D3_STS", BIT(14), 0},
334 {"PTIO_D3_STS", BIT(16), 0},
335 {"PMT_D3_STS", BIT(17), 0},
336 {"SMS1_D3_STS", BIT(18), 0},
337 {"SMS2_D3_STS", BIT(19), 0},
342 {"THC0_D3_STS", BIT(14), 1},
343 {"THC1_D3_STS", BIT(15), 1},
344 {"OSSE_SMT3_D3_STS", BIT(18), 0},
345 {"ACE_D3_STS", BIT(23), 0},
350 {"LPSS_VNN_REQ_STS", BIT(3), 1},
351 {"OSSE_VNN_REQ_STS", BIT(6), 1},
352 {"ESPISPI_VNN_REQ_STS", BIT(18), 1},
353 {"OSSE_SMT1_VNN_REQ_STS", BIT(30), 1},
358 {"NPK_VNN_REQ_STS", BIT(4), 1},
359 {"DFXAGG_VNN_REQ_STS", BIT(8), 0},
360 {"EXI_VNN_REQ_STS", BIT(9), 1},
361 {"P2D_VNN_REQ_STS", BIT(18), 1},
362 {"GBE_VNN_REQ_STS", BIT(19), 1},
363 {"SMB_VNN_REQ_STS", BIT(25), 1},
364 {"LPC_VNN_REQ_STS", BIT(26), 0},
365 {"ESE_VNN_REQ_STS", BIT(30), 1},
370 {"CSMERTC_VNN_REQ_STS", BIT(1), 1},
371 {"CSE_VNN_REQ_STS", BIT(4), 1},
372 {"ISH_VNN_REQ_STS", BIT(7), 1},
373 {"SMT1_VNN_REQ_STS", BIT(8), 1},
374 {"CLINK_VNN_REQ_STS", BIT(14), 1},
375 {"SMS1_VNN_REQ_STS", BIT(18), 1},
376 {"SMS2_VNN_REQ_STS", BIT(19), 1},
377 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
378 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
379 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
380 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
381 {"DISP_SHIM_VNN_REQ_STS", BIT(26), 1},
386 {"DTS0_VNN_REQ_STS", BIT(7), 0},
387 {"GPIOCOM5_VNN_REQ_STS", BIT(11), 1},
392 {"CPU_C10_REQ_STS", BIT(0), 0},
393 {"TS_OFF_REQ_STS", BIT(1), 0},
394 {"PNDE_MET_REQ_STS", BIT(2), 1},
395 {"PG5_PMA0_REQ_STS", BIT(3), 0},
396 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0},
397 {"VNN_SOC_REQ_STS", BIT(6), 1},
398 {"ISH_VNNAON_REQ_STS", BIT(7), 0},
399 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
400 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
401 {"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1},
402 {"PLT_GREATER_REQ_STS", BIT(11), 1},
403 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0},
404 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
405 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
406 {"EA_REQ_STS", BIT(15), 0},
407 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
408 {"BRK_EV_EN_REQ_STS", BIT(17), 0},
409 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
410 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
411 {"ARC_IDLE_REQ_STS", BIT(21), 0},
412 {"PG5_PMA1_REQ_STS", BIT(22), 0},
413 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
414 {"XDCI_ATTACHED_REQ_STS", BIT(24), 1},
415 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
416 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
417 {"PRE_WAKE0_REQ_STS", BIT(27), 1},
418 {"PRE_WAKE1_REQ_STS", BIT(28), 1},
419 {"PRE_WAKE2_REQ_STS", BIT(29), 1},
420 {"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1},
425 {"LSX_Wake0_STS", BIT(0), 0},
426 {"LSX_Wake1_STS", BIT(1), 0},
427 {"LSX_Wake2_STS", BIT(2), 0},
428 {"LSX_Wake3_STS", BIT(3), 0},
429 {"LSX_Wake4_STS", BIT(4), 0},
430 {"LSX_Wake5_STS", BIT(5), 0},
431 {"LSX_Wake6_STS", BIT(6), 0},
432 {"LSX_Wake7_STS", BIT(7), 0},
433 {"LPSS_Wake0_STS", BIT(8), 1},
434 {"LPSS_Wake1_STS", BIT(9), 1},
435 {"Int_Timer_SS_Wake0_STS", BIT(10), 1},
436 {"Int_Timer_SS_Wake1_STS", BIT(11), 1},
437 {"Int_Timer_SS_Wake2_STS", BIT(12), 1},
438 {"Int_Timer_SS_Wake3_STS", BIT(13), 1},
439 {"Int_Timer_SS_Wake4_STS", BIT(14), 1},
440 {"Int_Timer_SS_Wake5_STS", BIT(15), 1},