Lines Matching full:bit
64 {"AON2_OFF_STS", BIT(0)},
65 {"AON3_OFF_STS", BIT(1)},
66 {"AON4_OFF_STS", BIT(2)},
67 {"AON5_OFF_STS", BIT(3)},
68 {"AON1_OFF_STS", BIT(4)},
69 {"XTAL_LVM_OFF_STS", BIT(5)},
70 {"AON3_SPL_OFF_STS", BIT(9)},
71 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
72 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
73 {"G5X16FPW_0_PLL_OFF_STS", BIT(14)},
74 {"G5X16FPW_1_PLL_OFF_STS", BIT(15)},
75 {"G5X16FPW_2_PLL_OFF_STS", BIT(16)},
76 {"XTAL_AGGR_OFF_STS", BIT(17)},
77 {"USB2_PLL_OFF_STS", BIT(18)},
78 {"G5X16FPW_3_PLL_OFF_STS", BIT(19)},
79 {"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)},
80 {"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)},
81 {"FILTER_PLL_OFF_STS", BIT(22)},
82 {"FABRIC_PLL_OFF_STS", BIT(25)},
83 {"SOC_PLL_OFF_STS", BIT(26)},
84 {"PCIEFAB_PLL_OFF_STS", BIT(27)},
85 {"REF_PLL_OFF_STS", BIT(28)},
86 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)},
87 {"RTC_PLL_OFF_STS", BIT(31)},
92 {"PMC_PGD0_PG_STS", BIT(0)},
93 {"DMI_PGD0_PG_STS", BIT(1)},
94 {"ESPISPI_PGD0_PG_STS", BIT(2)},
95 {"XHCI_PGD0_PG_STS", BIT(3)},
96 {"SPA_PGD0_PG_STS", BIT(4)},
97 {"SPB_PGD0_PG_STS", BIT(5)},
98 {"SPC_PGD0_PG_STS", BIT(6)},
99 {"GBE_PGD0_PG_STS", BIT(7)},
100 {"SATA_PGD0_PG_STS", BIT(8)},
101 {"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)},
102 {"G5x16FPW_PGD0_PG_STS", BIT(10)},
103 {"FIA_D_PGD0_PG_STS", BIT(11)},
104 {"MPFPW2_PGD0_PG_STS", BIT(12)},
105 {"SPD_PGD0_PG_STS", BIT(13)},
106 {"LPSS_PGD0_PG_STS", BIT(14)},
107 {"LPC_PGD0_PG_STS", BIT(15)},
108 {"SMB_PGD0_PG_STS", BIT(16)},
109 {"ISH_PGD0_PG_STS", BIT(17)},
110 {"P2S_PGD0_PG_STS", BIT(18)},
111 {"NPK_PGD0_PG_STS", BIT(19)},
112 {"DMI3FPW_PGD0_PG_STS", BIT(20)},
113 {"GBETSN1_PGD0_PG_STS", BIT(21)},
114 {"FUSE_PGD0_PG_STS", BIT(22)},
115 {"FIACPCB_D_PGD0_PG_STS", BIT(23)},
116 {"FUSEGPSB_PGD0_PG_STS", BIT(24)},
117 {"XDCI_PGD0_PG_STS", BIT(25)},
118 {"EXI_PGD0_PG_STS", BIT(26)},
119 {"CSE_PGD0_PG_STS", BIT(27)},
120 {"KVMCC_PGD0_PG_STS", BIT(28)},
121 {"PMT_PGD0_PG_STS", BIT(29)},
122 {"CLINK_PGD0_PG_STS", BIT(30)},
123 {"PTIO_PGD0_PG_STS", BIT(31)},
128 {"USBR0_PGD0_PG_STS", BIT(0)},
129 {"SUSRAM_PGD0_PG_STS", BIT(1)},
130 {"SMT1_PGD0_PG_STS", BIT(2)},
131 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
132 {"SMS2_PGD0_PG_STS", BIT(4)},
133 {"SMS1_PGD0_PG_STS", BIT(5)},
134 {"CSMERTC_PGD0_PG_STS", BIT(6)},
135 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
136 {"SBR0_PGD0_PG_STS", BIT(8)},
137 {"SBR1_PGD0_PG_STS", BIT(9)},
138 {"SBR2_PGD0_PG_STS", BIT(10)},
139 {"SBR3_PGD0_PG_STS", BIT(11)},
140 {"MPFPW1_PGD0_PG_STS", BIT(12)},
141 {"SBR5_PGD0_PG_STS", BIT(13)},
142 {"FIA_X_PGD0_PG_STS", BIT(14)},
143 {"FIACPCB_X_PGD0_PG_STS", BIT(15)},
144 {"SBRG_PGD0_PG_STS", BIT(16)},
145 {"SOC_D2D_PGD1_PG_STS", BIT(17)},
146 {"PSF4_PGD0_PG_STS", BIT(18)},
147 {"CNVI_PGD0_PG_STS", BIT(19)},
148 {"UFSX2_PGD0_PG_STS", BIT(20)},
149 {"ENDBG_PGD0_PG_STS", BIT(21)},
150 {"DBG_PSF_PGD0_PG_STS", BIT(22)},
151 {"SBR6_PGD0_PG_STS", BIT(23)},
152 {"SOC_D2D_PGD2_PG_STS", BIT(24)},
153 {"NPK_PGD1_PG_STS", BIT(25)},
154 {"DMI3_PGD0_PG_STS", BIT(26)},
155 {"DBG_SBR_PGD0_PG_STS", BIT(27)},
156 {"SOC_D2D_PGD0_PG_STS", BIT(28)},
157 {"PSF6_PGD0_PG_STS", BIT(29)},
158 {"PSF7_PGD0_PG_STS", BIT(30)},
159 {"MPFPW3_PGD0_PG_STS", BIT(31)},
164 {"PSF8_PGD0_PG_STS", BIT(0)},
165 {"FIA_PGD0_PG_STS", BIT(1)},
166 {"SOC_D2D_PGD3_PG_STS", BIT(2)},
167 {"FIA_U_PGD0_PG_STS", BIT(3)},
168 {"TAM_PGD0_PG_STS", BIT(4)},
169 {"GBETSN_PGD0_PG_STS", BIT(5)},
170 {"TBTLSX_PGD0_PG_STS", BIT(6)},
171 {"THC0_PGD0_PG_STS", BIT(7)},
172 {"THC1_PGD0_PG_STS", BIT(8)},
173 {"PMC_PGD1_PG_STS", BIT(9)},
174 {"FIA_P5x16_PGD0_PG_STS", BIT(10)},
175 {"GNA_PGD0_PG_STS", BIT(11)},
176 {"ACE_PGD0_PG_STS", BIT(12)},
177 {"ACE_PGD1_PG_STS", BIT(13)},
178 {"ACE_PGD2_PG_STS", BIT(14)},
179 {"ACE_PGD3_PG_STS", BIT(15)},
180 {"ACE_PGD4_PG_STS", BIT(16)},
181 {"ACE_PGD5_PG_STS", BIT(17)},
182 {"ACE_PGD6_PG_STS", BIT(18)},
183 {"ACE_PGD7_PG_STS", BIT(19)},
184 {"ACE_PGD8_PG_STS", BIT(20)},
185 {"FIA_PGS_PGD0_PG_STS", BIT(21)},
186 {"FIACPCB_PGS_PGD0_PG_STS", BIT(22)},
187 {"FUSEPMSB_PGD0_PG_STS", BIT(23)},
192 {"CSMERTC_D3_STS", BIT(1)},
193 {"SUSRAM_D3_STS", BIT(2)},
194 {"CSE_D3_STS", BIT(4)},
195 {"KVMCC_D3_STS", BIT(5)},
196 {"USBR0_D3_STS", BIT(6)},
197 {"ISH_D3_STS", BIT(7)},
198 {"SMT1_D3_STS", BIT(8)},
199 {"SMT2_D3_STS", BIT(9)},
200 {"SMT3_D3_STS", BIT(10)},
201 {"GNA_D3_STS", BIT(12)},
202 {"CLINK_D3_STS", BIT(14)},
203 {"PTIO_D3_STS", BIT(16)},
204 {"PMT_D3_STS", BIT(17)},
205 {"SMS1_D3_STS", BIT(18)},
206 {"SMS2_D3_STS", BIT(19)},
211 {"GBETSN_D3_STS", BIT(13)},
212 {"THC0_D3_STS", BIT(14)},
213 {"THC1_D3_STS", BIT(15)},
214 {"ACE_D3_STS", BIT(23)},
219 {"DTS0_VNN_REQ_STS", BIT(7)},
220 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
243 {"RSVD64", BIT(0)},
244 {"RSVD65", BIT(1)},
245 {"RSVD66", BIT(2)},
246 {"RSVD67", BIT(3)},
247 {"RSVD68", BIT(4)},
248 {"GBETSN", BIT(5)},
249 {"TBTLSX", BIT(6)},
328 {"AON2_OFF_STS", BIT(0)},
329 {"AON3_OFF_STS", BIT(1)},
330 {"AON4_OFF_STS", BIT(2)},
331 {"AON2_SPL_OFF_STS", BIT(3)},
332 {"AONL_OFF_STS", BIT(4)},
333 {"XTAL_LVM_OFF_STS", BIT(5)},
334 {"AON5_ACRO_OFF_STS", BIT(6)},
335 {"AON6_ACRO_OFF_STS", BIT(7)},
336 {"USB3_PLL_OFF_STS", BIT(8)},
337 {"ACRO_OFF_STS", BIT(9)},
338 {"AUDIO_PLL_OFF_STS", BIT(10)},
339 {"MAIN_CRO_OFF_STS", BIT(11)},
340 {"MAIN_DIVIDER_OFF_STS", BIT(12)},
341 {"REF_PLL_NON_OC_OFF_STS", BIT(13)},
342 {"DMI_PLL_OFF_STS", BIT(14)},
343 {"PHY_EXT_INJ_OFF_STS", BIT(15)},
344 {"AON6_MCRO_OFF_STS", BIT(16)},
345 {"XTAL_AGGR_OFF_STS", BIT(17)},
346 {"USB2_PLL_OFF_STS", BIT(18)},
347 {"TSN0_PLL_OFF_STS", BIT(19)},
348 {"TSN1_PLL_OFF_STS", BIT(20)},
349 {"GBE_PLL_OFF_STS", BIT(21)},
350 {"SATA_PLL_OFF_STS", BIT(22)},
351 {"PCIE0_PLL_OFF_STS", BIT(23)},
352 {"PCIE1_PLL_OFF_STS", BIT(24)},
353 {"PCIE2_PLL_OFF_STS", BIT(26)},
354 {"PCIE3_PLL_OFF_STS", BIT(27)},
355 {"REF_PLL_OFF_STS", BIT(28)},
356 {"PCIE4_PLL_OFF_STS", BIT(29)},
357 {"PCIE5_PLL_OFF_STS", BIT(30)},
358 {"REF38P4_PLL_OFF_STS", BIT(31)},
363 {"PMC_PGD0_PG_STS", BIT(0)},
364 {"DMI_PGD0_PG_STS", BIT(1)},
365 {"ESPISPI_PGD0_PG_STS", BIT(2)},
366 {"XHCI_PGD0_PG_STS", BIT(3)},
367 {"SPA_PGD0_PG_STS", BIT(4)},
368 {"SPB_PGD0_PG_STS", BIT(5)},
369 {"SPC_PGD0_PG_STS", BIT(6)},
370 {"GBE_PGD0_PG_STS", BIT(7)},
371 {"SATA_PGD0_PG_STS", BIT(8)},
372 {"FIA_X_PGD0_PG_STS", BIT(9)},
373 {"MPFPW4_PGD0_PG_STS", BIT(10)},
374 {"EAH_PGD0_PG_STS", BIT(11)},
375 {"MPFPW1_PGD0_PG_STS", BIT(12)},
376 {"SPD_PGD0_PG_STS", BIT(13)},
377 {"LPSS_PGD0_PG_STS", BIT(14)},
378 {"LPC_PGD0_PG_STS", BIT(15)},
379 {"SMB_PGD0_PG_STS", BIT(16)},
380 {"ISH_PGD0_PG_STS", BIT(17)},
381 {"P2S_PGD0_PG_STS", BIT(18)},
382 {"NPK_PGD0_PG_STS", BIT(19)},
383 {"U3FPW1_PGD0_PG_STS", BIT(20)},
384 {"PECI_PGD0_PG_STS", BIT(21)},
385 {"FUSE_PGD0_PG_STS", BIT(22)},
386 {"SBR8_PGD0_PG_STS", BIT(23)},
387 {"EXE_PGD0_PG_STS", BIT(24)},
388 {"XDCI_PGD0_PG_STS", BIT(25)},
389 {"EXI_PGD0_PG_STS", BIT(26)},
390 {"CSE_PGD0_PG_STS", BIT(27)},
391 {"KVMCC_PGD0_PG_STS", BIT(28)},
392 {"PMT_PGD0_PG_STS", BIT(29)},
393 {"CLINK_PGD0_PG_STS", BIT(30)},
394 {"PTIO_PGD0_PG_STS", BIT(31)},
399 {"USBR0_PGD0_PG_STS", BIT(0)},
400 {"SUSRAM_PGD0_PG_STS", BIT(1)},
401 {"SMT1_PGD0_PG_STS", BIT(2)},
402 {"SMT4_PGD0_PG_STS", BIT(3)},
403 {"SMS2_PGD0_PG_STS", BIT(4)},
404 {"SMS1_PGD0_PG_STS", BIT(5)},
405 {"CSMERTC_PGD0_PG_STS", BIT(6)},
406 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
407 {"SBR0_PGD0_PG_STS", BIT(8)},
408 {"SBR1_PGD0_PG_STS", BIT(9)},
409 {"SBR2_PGD0_PG_STS", BIT(10)},
410 {"SBR3_PGD0_PG_STS", BIT(11)},
411 {"SBR4_PGD0_PG_STS", BIT(12)},
412 {"SBR5_PGD0_PG_STS", BIT(13)},
413 {"MPFPW3_PGD0_PG_STS", BIT(14)},
414 {"PSF1_PGD0_PG_STS", BIT(15)},
415 {"PSF2_PGD0_PG_STS", BIT(16)},
416 {"PSF3_PGD0_PG_STS", BIT(17)},
417 {"PSF4_PGD0_PG_STS", BIT(18)},
418 {"CNVI_PGD0_PG_STS", BIT(19)},
419 {"DMI3_PGD0_PG_STS", BIT(20)},
420 {"ENDBG_PGD0_PG_STS", BIT(21)},
421 {"DBG_SBR_PGD0_PG_STS", BIT(22)},
422 {"SBR6_PGD0_PG_STS", BIT(23)},
423 {"SBR7_PGD0_PG_STS", BIT(24)},
424 {"NPK_PGD1_PG_STS", BIT(25)},
425 {"U3FPW3_PGD0_PG_STS", BIT(26)},
426 {"MPFPW2_PGD0_PG_STS", BIT(27)},
427 {"MPFPW7_PGD0_PG_STS", BIT(28)},
428 {"GBETSN1_PGD0_PG_STS", BIT(29)},
429 {"PSF7_PGD0_PG_STS", BIT(30)},
430 {"FIA2_PGD0_PG_STS", BIT(31)},
435 {"U3FPW2_PGD0_PG_STS", BIT(0)},
436 {"FIA_PGD0_PG_STS", BIT(1)},
437 {"FIACPCB_X_PGD0_PG_STS", BIT(2)},
438 {"FIA1_PGD0_PG_STS", BIT(3)},
439 {"TAM_PGD0_PG_STS", BIT(4)},
440 {"GBETSN_PGD0_PG_STS", BIT(5)},
441 {"SBR9_PGD0_PG_STS", BIT(6)},
442 {"THC0_PGD0_PG_STS", BIT(7)},
443 {"THC1_PGD0_PG_STS", BIT(8)},
444 {"PMC_PGD1_PG_STS", BIT(9)},
445 {"DBC_PGD0_PG_STS", BIT(10)},
446 {"DBG_PSF_PGD0_PG_STS", BIT(11)},
447 {"SPF_PGD0_PG_STS", BIT(12)},
448 {"ACE_PGD0_PG_STS", BIT(13)},
449 {"ACE_PGD1_PG_STS", BIT(14)},
450 {"ACE_PGD2_PG_STS", BIT(15)},
451 {"ACE_PGD3_PG_STS", BIT(16)},
452 {"ACE_PGD4_PG_STS", BIT(17)},
453 {"ACE_PGD5_PG_STS", BIT(18)},
454 {"ACE_PGD6_PG_STS", BIT(19)},
455 {"ACE_PGD7_PG_STS", BIT(20)},
456 {"SPE_PGD0_PG_STS", BIT(21)},
457 {"MPFPW5_PG_STS", BIT(22)},
462 {"SPF_D3_STS", BIT(0)},
463 {"LPSS_D3_STS", BIT(3)},
464 {"XDCI_D3_STS", BIT(4)},
465 {"XHCI_D3_STS", BIT(5)},
466 {"SPA_D3_STS", BIT(12)},
467 {"SPB_D3_STS", BIT(13)},
468 {"SPC_D3_STS", BIT(14)},
469 {"SPD_D3_STS", BIT(15)},
470 {"SPE_D3_STS", BIT(16)},
471 {"ESPISPI_D3_STS", BIT(18)},
472 {"SATA_D3_STS", BIT(20)},
473 {"PSTH_D3_STS", BIT(21)},
474 {"DMI_D3_STS", BIT(22)},
479 {"GBETSN1_D3_STS", BIT(14)},
480 {"GBE_D3_STS", BIT(19)},
481 {"ITSS_D3_STS", BIT(23)},
482 {"P2S_D3_STS", BIT(24)},
483 {"CNVI_D3_STS", BIT(27)},
488 {"CSMERTC_D3_STS", BIT(1)},
489 {"SUSRAM_D3_STS", BIT(2)},
490 {"CSE_D3_STS", BIT(4)},
491 {"KVMCC_D3_STS", BIT(5)},
492 {"USBR0_D3_STS", BIT(6)},
493 {"ISH_D3_STS", BIT(7)},
494 {"SMT1_D3_STS", BIT(8)},
495 {"SMT2_D3_STS", BIT(9)},
496 {"SMT3_D3_STS", BIT(10)},
497 {"SMT4_D3_STS", BIT(11)},
498 {"SMT5_D3_STS", BIT(12)},
499 {"SMT6_D3_STS", BIT(13)},
500 {"CLINK_D3_STS", BIT(14)},
501 {"PTIO_D3_STS", BIT(16)},
502 {"PMT_D3_STS", BIT(17)},
503 {"SMS1_D3_STS", BIT(18)},
504 {"SMS2_D3_STS", BIT(19)},
509 {"ESE_D3_STS", BIT(3)},
510 {"GBETSN_D3_STS", BIT(13)},
511 {"THC0_D3_STS", BIT(14)},
512 {"THC1_D3_STS", BIT(15)},
513 {"ACE_D3_STS", BIT(23)},
518 {"FIA_VNN_REQ_STS", BIT(17)},
519 {"ESPISPI_VNN_REQ_STS", BIT(18)},
524 {"NPK_VNN_REQ_STS", BIT(4)},
525 {"DFXAGG_VNN_REQ_STS", BIT(8)},
526 {"EXI_VNN_REQ_STS", BIT(9)},
527 {"GBE_VNN_REQ_STS", BIT(19)},
528 {"SMB_VNN_REQ_STS", BIT(25)},
529 {"LPC_VNN_REQ_STS", BIT(26)},
530 {"CNVI_VNN_REQ_STS", BIT(27)},
535 {"FIA2_VNN_REQ_STS", BIT(0)},
536 {"CSMERTC_VNN_REQ_STS", BIT(1)},
537 {"CSE_VNN_REQ_STS", BIT(4)},
538 {"ISH_VNN_REQ_STS", BIT(7)},
539 {"SMT1_VNN_REQ_STS", BIT(8)},
540 {"SMT4_VNN_REQ_STS", BIT(11)},
541 {"CLINK_VNN_REQ_STS", BIT(14)},
542 {"SMS1_VNN_REQ_STS", BIT(18)},
543 {"SMS2_VNN_REQ_STS", BIT(19)},
544 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
545 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
546 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
547 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
548 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
553 {"ESE_VNN_REQ_STS", BIT(3)},
554 {"DTS0_VNN_REQ_STS", BIT(7)},
555 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
556 {"FIA1_VNN_REQ_STS", BIT(12)},
561 {"CPU_C10_REQ_STS", BIT(0)},
562 {"TS_OFF_REQ_STS", BIT(1)},
563 {"PNDE_MET_REQ_STS", BIT(2)},
564 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
565 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)},
566 {"ISH_VNNAON_REQ_STS", BIT(7)},
567 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},
568 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},
569 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},
570 {"PLT_GREATER_REQ_STS", BIT(11)},
571 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
572 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
573 {"EA_REQ_STS", BIT(15)},
574 {"DMI_CLKREQ_B_REQ_STS", BIT(16)},
575 {"BRK_EV_EN_REQ_STS", BIT(17)},
576 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
577 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
578 {"ARC_IDLE_REQ_STS", BIT(21)},
579 {"DMI_IN_REQ_STS", BIT(22)},
580 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
581 {"XDCI_ATTACHED_REQ_STS", BIT(24)},
582 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
583 {"PRE_WAKE0_REQ_STS", BIT(27)},
584 {"PRE_WAKE1_REQ_STS", BIT(28)},
585 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
586 {"CNVI_V1P05_REQ_STS", BIT(31)},
591 {"LSX_Wake0_STS", BIT(0)},
592 {"LSX_Wake1_STS", BIT(1)},
593 {"LSX_Wake2_STS", BIT(2)},
594 {"LSX_Wake3_STS", BIT(3)},
595 {"LSX_Wake4_STS", BIT(4)},
596 {"LSX_Wake5_STS", BIT(5)},
597 {"LSX_Wake6_STS", BIT(6)},
598 {"LSX_Wake7_STS", BIT(7)},
599 {"Int_Timer_SS_Wake0_STS", BIT(8)},
600 {"Int_Timer_SS_Wake1_STS", BIT(9)},
601 {"Int_Timer_SS_Wake0_STS", BIT(10)},
602 {"Int_Timer_SS_Wake1_STS", BIT(11)},
603 {"Int_Timer_SS_Wake2_STS", BIT(12)},
604 {"Int_Timer_SS_Wake3_STS", BIT(13)},
605 {"Int_Timer_SS_Wake4_STS", BIT(14)},
606 {"Int_Timer_SS_Wake5_STS", BIT(15)},