pinctrl/tegra/pinctrl-tegra.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
28 	/* Array of size soc->ngroups */
53 	/* argument: Integer, range is HW-dependant */
55 	/* argument: Integer, range is HW-dependant */
57 	/* argument: Integer, range is HW-dependant */
59 	/* argument: Integer, range is HW-dependant */
61 	/* argument: Integer, range is HW-dependant */
83  * struct tegra_function - Tegra pinctrl mux function
95  * struct tegra_pingroup - Tegra pin group
103  * @mux_bank:		Mux register bank.
105  * @pupd_reg:		Pull-up/down register offset.
106  * @pupd_bank:		Pull-up/down register bank.
107  * @pupd_bit:		Pull-up/down register bit.
108  * @tri_reg:		Tri-state register offset.
109  * @tri_bank:		Tri-state register bank.
110  * @tri_bit:		Tri-state register bit.
111  * @einput_bit:		Enable-input register bit.
112  * @odrain_bit:		Open-drain register bit.
119  * @drv_bank:		Drive fields register bank.
125  * @drvdn_width:	Drive Down field width.
127  * @drvup_width:	Drive Up field width.
129  * @slwr_width:		Slew Rising field width.
131  * @slwf_width:		Slew Falling field width.
136  * -1 in a *_reg field means that feature is unsupported for this group.
137  * *_bank and *_reg values are irrelevant when *_reg is -1.
138  * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
143  * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
186  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
188  * @gpio_compatible:	Device-tree GPIO compatible string.
198  * @hsm_in_mux:		High-speed mode field. Only applicable to devices with one pin per group.