Lines Matching +full:ps2 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L Pin Control and GPIO driver core
11 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
37 #define DRV_NAME "pinctrl-rzg2l"
62 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
63 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
107 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
183 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
188 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
220 * struct rzg2l_register_offsets - specific register offsets
232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
249 * struct rzg2l_hwcfg - hardware configuration data structure
305 * struct rzg2l_pinctrl_pin_settings - pin data
315 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
377 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
378 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
482 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
487 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
490 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
491 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
492 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
493 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
502 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
504 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_set_pfc_mode()
505 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
507 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
509 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
511 /* Temporarily switch to GPIO mode with PMC register */ in rzg2l_pinctrl_set_pfc_mode()
512 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
513 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
516 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
518 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
521 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
522 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
524 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
526 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
534 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
542 return -EINVAL; in rzg2l_pinctrl_set_mux()
545 return -EINVAL; in rzg2l_pinctrl_set_mux()
547 psel_val = func->data; in rzg2l_pinctrl_set_mux()
548 pins = group->grp.pins; in rzg2l_pinctrl_set_mux()
550 for (i = 0; i < group->grp.npins; i++) { in rzg2l_pinctrl_set_mux()
551 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
555 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
556 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
558 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
574 return -ENOMEM; in rzg2l_map_add_config()
576 map->type = type; in rzg2l_map_add_config()
577 map->data.configs.group_or_pin = group_or_pin; in rzg2l_map_add_config()
578 map->data.configs.configs = cfgs; in rzg2l_map_add_config()
579 map->data.configs.num_configs = num_configs; in rzg2l_map_add_config()
609 num_pinmux = pinmux->length / sizeof(u32); in rzg2l_dt_subnode_to_map()
612 if (ret == -EINVAL) { in rzg2l_dt_subnode_to_map()
615 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
625 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
627 return -EINVAL; in rzg2l_dt_subnode_to_map()
635 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
636 ret = -ENODEV; in rzg2l_dt_subnode_to_map()
651 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
671 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
672 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
674 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
676 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
692 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
695 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
699 name = np->name; in rzg2l_dt_subnode_to_map()
712 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
732 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
739 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
746 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
800 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
801 ret = -EINVAL; in rzg2l_dt_node_to_map()
816 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
817 return -EINVAL; in rzg2l_validate_gpio_pin()
819 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_gpio_pin()
821 return -EINVAL; in rzg2l_validate_gpio_pin()
829 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
831 /* handle _L/_H for 32-bit register read/write */ in rzg2l_read_pin_config()
833 bit -= 4; in rzg2l_read_pin_config()
843 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
847 /* handle _L/_H for 32-bit register read/write */ in rzg2l_rmw_pin_config()
849 bit -= 4; in rzg2l_rmw_pin_config()
853 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
856 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
862 return SD_CH(regs->sd_ch, 0); in rzg2l_caps_to_pwr_reg()
864 return SD_CH(regs->sd_ch, 1); in rzg2l_caps_to_pwr_reg()
866 return ETH_POC(regs->eth_poc, 0); in rzg2l_caps_to_pwr_reg()
868 return ETH_POC(regs->eth_poc, 1); in rzg2l_caps_to_pwr_reg()
872 return -EINVAL; in rzg2l_caps_to_pwr_reg()
877 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
878 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_get_power_source()
883 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
889 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
899 return -EINVAL; in rzg2l_get_power_source()
905 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
906 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_set_power_source()
911 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
921 return -EINVAL; in rzg2l_set_power_source()
928 return -EINVAL; in rzg2l_set_power_source()
935 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
936 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
972 return hwcfg->iolh_groupa_ua[val]; in rzg2l_iolh_val_to_ua()
975 return hwcfg->iolh_groupb_ua[val]; in rzg2l_iolh_val_to_ua()
978 return hwcfg->iolh_groupc_ua[val]; in rzg2l_iolh_val_to_ua()
991 array = &hwcfg->iolh_groupa_ua[ps_index]; in rzg2l_iolh_ua_to_val()
994 array = &hwcfg->iolh_groupb_ua[ps_index]; in rzg2l_iolh_ua_to_val()
997 array = &hwcfg->iolh_groupc_ua[ps_index]; in rzg2l_iolh_ua_to_val()
1000 return -EINVAL; in rzg2l_iolh_ua_to_val()
1007 return -EINVAL; in rzg2l_iolh_ua_to_val()
1014 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
1019 array = hwcfg->iolh_groupa_ua; in rzg2l_ds_is_supported()
1022 array = hwcfg->iolh_groupb_ua; in rzg2l_ds_is_supported()
1025 array = hwcfg->iolh_groupc_ua; in rzg2l_ds_is_supported()
1044 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1048 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1049 return -EINVAL; in rzg2l_pin_to_oen_bit()
1060 return -EINVAL; in rzg2l_pin_to_oen_bit()
1071 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1084 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1085 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1090 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1091 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1098 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1102 return -EINVAL; in rzg3s_pin_to_oen_bit()
1106 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1107 return -EINVAL; in rzg3s_pin_to_oen_bit()
1110 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1124 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1137 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1138 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1143 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1144 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1162 return -EINVAL; in rzg2l_hw_to_bias_param()
1178 return -EINVAL; in rzg2l_bias_param_to_hw()
1195 return -EINVAL; in rzv2h_hw_to_bias_param()
1211 return -EINVAL; in rzv2h_bias_param_to_hw()
1219 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1223 if (!strcmp(pin_desc->name, pin_names[i])) in rzv2h_pin_to_oen_bit()
1237 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1242 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1243 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzv2h_oen_write()
1249 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1250 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1256 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1257 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1258 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1259 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1260 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1270 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1271 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
1273 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_get()
1281 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1291 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1297 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1300 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1305 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1306 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1307 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_get()
1308 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1310 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1322 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1331 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1334 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1339 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1347 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1348 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1355 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; in rzg2l_pinctrl_pinconf_get()
1364 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1365 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1379 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_get()
1380 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1383 arg = hwcfg->iolh_groupb_oi[index]; in rzg2l_pinctrl_pinconf_get()
1390 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1394 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1396 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1401 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1405 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1410 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1416 return -ENOTSUPP; in rzg2l_pinctrl_pinconf_get()
1430 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
1431 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1432 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set()
1433 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_set()
1441 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1451 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1461 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1468 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1469 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1470 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1471 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1482 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1491 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1493 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1501 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1502 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1506 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) in rzg2l_pinctrl_pinconf_set()
1510 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1517 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1518 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1524 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_set()
1525 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1527 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { in rzg2l_pinctrl_pinconf_set()
1528 if (arg == hwcfg->iolh_groupb_oi[index]) in rzg2l_pinctrl_pinconf_set()
1531 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) in rzg2l_pinctrl_pinconf_set()
1532 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1540 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1548 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1555 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1558 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1563 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1568 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1571 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1580 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1588 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1597 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1645 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_group_get()
1681 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1682 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_request()
1698 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1700 /* Select GPIO mode in PMC Register */ in rzg2l_gpio_request()
1701 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1703 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1705 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1713 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1714 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set_direction()
1720 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1722 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1726 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1728 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1734 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1735 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_direction()
1739 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1742 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1765 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1766 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set()
1772 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1774 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1777 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1779 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1781 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1798 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1799 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get()
1804 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1808 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1810 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
1812 return -EINVAL; in rzg2l_gpio_get()
1821 virq = irq_find_mapping(chip->irq.domain, offset); in rzg2l_gpio_free()
1826 * Set the GPIO as an input to ensure that the next GPIO request won't in rzg2l_gpio_free()
1827 * drive the GPIO pin as an output. in rzg2l_gpio_free()
1957 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
2036 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2403 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2404 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2405 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_gpioint()
2411 return -EINVAL; in rzg2l_gpio_get_gpioint()
2416 if (port >= data->n_ports || in rzg2l_gpio_get_gpioint()
2417 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) in rzg2l_gpio_get_gpioint()
2418 return -EINVAL; in rzg2l_gpio_get_gpioint()
2422 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); in rzg2l_gpio_get_gpioint()
2430 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2431 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_irq_endisable()
2437 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2439 bit -= 4; in rzg2l_gpio_irq_endisable()
2443 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2448 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2483 seq_puts(p, dev_name(gc->parent)); in rzg2l_gpio_irq_print_chip()
2493 if (!data->parent_data) in rzg2l_gpio_irq_set_wake()
2494 return -EOPNOTSUPP; in rzg2l_gpio_irq_set_wake()
2501 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2503 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2509 .name = "rzg2l-gpio",
2526 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2527 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_interrupt_input_mode()
2533 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2562 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2563 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2564 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2566 ret = -ENOSPC; in rzg2l_gpio_child_to_parent_hwirq()
2571 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2572 irq += pctrl->data->hwcfg->tint_start_index; in rzg2l_gpio_child_to_parent_hwirq()
2586 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2594 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2597 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2599 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2600 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2606 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2614 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2618 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2621 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2639 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2642 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2643 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2644 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2645 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2658 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2662 for (offset = 0; offset < chip->ngpio; offset++) { in rzg2l_init_irq_valid_mask()
2668 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2670 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2677 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2680 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2682 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2684 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2686 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2688 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2689 if (!cache->p) in rzg2l_pinctrl_reg_cache_alloc()
2690 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2692 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2693 if (!cache->pm) in rzg2l_pinctrl_reg_cache_alloc()
2694 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2696 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2697 if (!cache->pmc) in rzg2l_pinctrl_reg_cache_alloc()
2698 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2700 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2701 if (!cache->pfc) in rzg2l_pinctrl_reg_cache_alloc()
2702 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2705 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2707 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2709 if (!cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2710 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2712 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2714 if (!cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2715 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2717 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), in rzg2l_pinctrl_reg_cache_alloc()
2719 if (!cache->pupd[i]) in rzg2l_pinctrl_reg_cache_alloc()
2720 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2723 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2724 sizeof(*dedicated_cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2726 if (!dedicated_cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2727 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2729 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2730 sizeof(*dedicated_cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2732 if (!dedicated_cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2733 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2736 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2737 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2744 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2745 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2746 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2755 return -ENXIO; in rzg2l_gpio_register()
2760 return -EPROBE_DEFER; in rzg2l_gpio_register()
2762 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); in rzg2l_gpio_register()
2764 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2769 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2770 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2771 "gpio-ranges does not match selected SOC\n"); in rzg2l_gpio_register()
2773 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2774 chip->request = rzg2l_gpio_request; in rzg2l_gpio_register()
2775 chip->free = rzg2l_gpio_free; in rzg2l_gpio_register()
2776 chip->get_direction = rzg2l_gpio_get_direction; in rzg2l_gpio_register()
2777 chip->direction_input = rzg2l_gpio_direction_input; in rzg2l_gpio_register()
2778 chip->direction_output = rzg2l_gpio_direction_output; in rzg2l_gpio_register()
2779 chip->get = rzg2l_gpio_get; in rzg2l_gpio_register()
2780 chip->set = rzg2l_gpio_set; in rzg2l_gpio_register()
2781 chip->label = name; in rzg2l_gpio_register()
2782 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2783 chip->owner = THIS_MODULE; in rzg2l_gpio_register()
2784 chip->base = -1; in rzg2l_gpio_register()
2785 chip->ngpio = of_args.args[2]; in rzg2l_gpio_register()
2787 girq = &chip->irq; in rzg2l_gpio_register()
2789 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2790 girq->parent_domain = parent_domain; in rzg2l_gpio_register()
2791 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; in rzg2l_gpio_register()
2792 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; in rzg2l_gpio_register()
2793 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; in rzg2l_gpio_register()
2794 girq->init_valid_mask = rzg2l_init_irq_valid_mask; in rzg2l_gpio_register()
2796 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2797 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2798 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2799 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2800 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2801 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2802 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2804 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2806 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2813 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2819 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2820 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2821 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2822 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2823 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2824 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2825 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2826 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2827 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2829 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2833 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2835 return -ENOMEM; in rzg2l_pinctrl_register()
2837 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2840 return -ENOMEM; in rzg2l_pinctrl_register()
2842 pctrl->pins = pins; in rzg2l_pinctrl_register()
2843 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2845 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2847 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2850 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2859 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2860 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2863 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2864 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2868 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2870 if (!pctrl->settings) in rzg2l_pinctrl_register()
2871 return -ENOMEM; in rzg2l_pinctrl_register()
2873 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2875 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2880 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2888 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2889 &pctrl->pctl); in rzg2l_pinctrl_register()
2891 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2893 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2895 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2899 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2924 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2926 return -ENOMEM; in rzg2l_pinctrl_probe()
2928 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2930 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2931 if (!pctrl->data) in rzg2l_pinctrl_probe()
2932 return -EINVAL; in rzg2l_pinctrl_probe()
2934 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2935 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2936 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2938 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2939 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2940 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2941 "failed to enable GPIO clk\n"); in rzg2l_pinctrl_probe()
2944 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2945 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2946 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2947 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2955 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2961 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2962 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2970 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2980 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
2984 * HW manual (section "Operation for GPIO Function"). in rzg2l_pinctrl_pm_setup_regs()
2986 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
2988 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
2989 cache->iolh[0][port]); in rzg2l_pinctrl_pm_setup_regs()
2991 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2992 cache->iolh[1][port]); in rzg2l_pinctrl_pm_setup_regs()
2997 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
2998 cache->pupd[0][port]); in rzg2l_pinctrl_pm_setup_regs()
3000 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
3001 cache->pupd[1][port]); in rzg2l_pinctrl_pm_setup_regs()
3005 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
3006 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
3009 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
3010 cache->ien[0][port]); in rzg2l_pinctrl_pm_setup_regs()
3012 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3013 cache->ien[1][port]); in rzg2l_pinctrl_pm_setup_regs()
3021 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3026 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same in rzg2l_pinctrl_pm_setup_dedicated_regs()
3029 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3035 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3037 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3038 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3054 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3055 cache->iolh[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3058 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3059 cache->ien[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3065 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3066 cache->iolh[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3070 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3071 cache->ien[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3080 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
3083 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3084 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
3095 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
3100 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3102 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
3105 if (!(cache->pmc[port] & BIT(pin))) in rzg2l_pinctrl_pm_setup_pfc()
3108 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_pm_setup_pfc()
3110 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3112 /* Temporarily switch to GPIO mode with PMC register */ in rzg2l_pinctrl_pm_setup_pfc()
3114 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3118 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); in rzg2l_pinctrl_pm_setup_pfc()
3119 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3123 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3127 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
3128 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3134 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
3135 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_suspend_noirq()
3136 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
3142 if (regs->sd_ch) in rzg2l_pinctrl_suspend_noirq()
3143 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
3144 if (regs->eth_poc) in rzg2l_pinctrl_suspend_noirq()
3145 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
3148 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
3149 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
3151 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
3152 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
3162 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
3163 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_resume_noirq()
3164 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
3167 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
3168 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
3173 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
3174 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
3176 if (regs->sd_ch) in rzg2l_pinctrl_resume_noirq()
3177 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
3178 if (regs->eth_poc) in rzg2l_pinctrl_resume_noirq()
3179 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
3192 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3195 /* Set the PWPR register to be write-protected */ in rzg2l_pwpr_pfc_lock_unlock()
3196 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3197 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3200 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3201 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3207 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3211 /* Set the PWPR register to be write-protected */ in rzv2h_pwpr_pfc_lock_unlock()
3212 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3213 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3216 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3217 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3377 .compatible = "renesas,r9a07g043-pinctrl",
3381 .compatible = "renesas,r9a07g044-pinctrl",
3385 .compatible = "renesas,r9a08g045-pinctrl",
3389 .compatible = "renesas,r9a09g047-pinctrl",
3393 .compatible = "renesas,r9a09g057-pinctrl",
3419 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
3420 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");