Lines Matching +full:8 +full:- +full:pin
1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
26 #define DRIVER_NAME "pinctrl-rza2"
28 #define RZA2_PINS_PER_PORT 8
33 * Use 16 lower bits [15:0] for pin identifier
34 * Use 16 higher bits [31:16] for pin mux function
55 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
56 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
57 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
58 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
59 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
60 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */ argument
62 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
63 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
64 #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
65 #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
66 #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
76 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin, in rza2_set_pin_function() argument
83 /* Set pin to 'Non-use (Hi-z input protection)' */ in rza2_set_pin_function()
85 mask16 = RZA2_PDR_MASK << (pin * 2); in rza2_set_pin_function()
91 reg8 &= ~BIT(pin); in rza2_set_pin_function()
98 /* Set Pin function (interrupt disabled, ISEL=0) */ in rza2_set_pin_function()
99 writeb(func, pfc_base + RZA2_PFS(port, pin)); in rza2_set_pin_function()
105 /* Port Mode : Peripheral module pin functions */ in rza2_set_pin_function()
107 reg8 |= BIT(pin); in rza2_set_pin_function()
115 u8 pin = RZA2_PIN_ID_TO_PIN(offset); in rza2_pin_to_gpio() local
120 mask16 = RZA2_PDR_MASK << (pin * 2); in rza2_pin_to_gpio()
124 reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */ in rza2_pin_to_gpio()
126 reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */ in rza2_pin_to_gpio()
135 u8 pin = RZA2_PIN_ID_TO_PIN(offset); in rza2_chip_get_direction() local
138 reg16 = readw(priv->base + RZA2_PDR(port)); in rza2_chip_get_direction()
139 reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK; in rza2_chip_get_direction()
148 * This GPIO controller has a default Hi-Z state that is not input or in rza2_chip_get_direction()
149 * output, so force the pin to input now. in rza2_chip_get_direction()
151 rza2_pin_to_gpio(priv->base, offset, 1); in rza2_chip_get_direction()
161 rza2_pin_to_gpio(priv->base, offset, 1); in rza2_chip_direction_input()
170 u8 pin = RZA2_PIN_ID_TO_PIN(offset); in rza2_chip_get() local
172 return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); in rza2_chip_get()
180 u8 pin = RZA2_PIN_ID_TO_PIN(offset); in rza2_chip_set() local
183 new_value = readb(priv->base + RZA2_PODR(port)); in rza2_chip_set()
186 new_value |= BIT(pin); in rza2_chip_set()
188 new_value &= ~BIT(pin); in rza2_chip_set()
190 writeb(new_value, priv->base + RZA2_PODR(port)); in rza2_chip_set()
199 rza2_pin_to_gpio(priv->base, offset, 0); in rza2_chip_direction_output()
232 .base = -1,
244 struct device_node *np = priv->dev->of_node; in rza2_gpio_register()
248 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); in rza2_gpio_register()
250 return -ENOMEM; in rza2_gpio_register()
252 chip.parent = priv->dev; in rza2_gpio_register()
253 chip.ngpio = priv->npins; in rza2_gpio_register()
255 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, in rza2_gpio_register()
258 dev_err(priv->dev, "Unable to parse gpio-ranges\n"); in rza2_gpio_register()
266 (of_args.args[2] != priv->npins)) { in rza2_gpio_register()
267 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n"); in rza2_gpio_register()
268 return -EINVAL; in rza2_gpio_register()
270 priv->gpio_range.id = 0; in rza2_gpio_register()
271 priv->gpio_range.pin_base = priv->gpio_range.base = 0; in rza2_gpio_register()
272 priv->gpio_range.npins = priv->npins; in rza2_gpio_register()
273 priv->gpio_range.name = chip.label; in rza2_gpio_register()
274 priv->gpio_range.gc = &chip; in rza2_gpio_register()
277 ret = devm_gpiochip_add_data(priv->dev, &chip, priv); in rza2_gpio_register()
281 /* Register pin range with pinctrl core */ in rza2_gpio_register()
282 pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range); in rza2_gpio_register()
284 dev_dbg(priv->dev, "Registered gpio controller\n"); in rza2_gpio_register()
295 pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); in rza2_pinctrl_register()
297 return -ENOMEM; in rza2_pinctrl_register()
299 priv->pins = pins; in rza2_pinctrl_register()
300 priv->desc.pins = pins; in rza2_pinctrl_register()
301 priv->desc.npins = priv->npins; in rza2_pinctrl_register()
303 for (i = 0; i < priv->npins; i++) { in rza2_pinctrl_register()
308 ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, in rza2_pinctrl_register()
309 &priv->pctl); in rza2_pinctrl_register()
311 dev_err(priv->dev, "pinctrl registration failed\n"); in rza2_pinctrl_register()
315 ret = pinctrl_enable(priv->pctl); in rza2_pinctrl_register()
317 dev_err(priv->dev, "pinctrl enable failed\n"); in rza2_pinctrl_register()
323 dev_err(priv->dev, "GPIO registration failed\n"); in rza2_pinctrl_register()
331 * For each DT node, create a single pin mapping. That pin mapping will only
349 dev_info(priv->dev, "Missing pinmux property\n"); in rza2_dt_node_to_map()
350 return -ENOENT; in rza2_dt_node_to_map()
352 npins = of_pins->length / sizeof(u32); in rza2_dt_node_to_map()
354 pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL); in rza2_dt_node_to_map()
355 psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val), in rza2_dt_node_to_map()
357 pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL); in rza2_dt_node_to_map()
359 return -ENOMEM; in rza2_dt_node_to_map()
361 /* Collect pin locations and mux settings from DT properties */ in rza2_dt_node_to_map()
372 mutex_lock(&priv->mutex); in rza2_dt_node_to_map()
374 /* Register a single pin group listing all the pins we read from DT */ in rza2_dt_node_to_map()
375 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL); in rza2_dt_node_to_map()
385 pin_fn[0] = np->name; in rza2_dt_node_to_map()
386 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, in rza2_dt_node_to_map()
393 dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins); in rza2_dt_node_to_map()
399 ret = -ENOMEM; in rza2_dt_node_to_map()
403 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in rza2_dt_node_to_map()
404 (*map)->data.mux.group = np->name; in rza2_dt_node_to_map()
405 (*map)->data.mux.function = np->name; in rza2_dt_node_to_map()
408 mutex_unlock(&priv->mutex); in rza2_dt_node_to_map()
419 mutex_unlock(&priv->mutex); in rza2_dt_node_to_map()
421 dev_err(priv->dev, "Unable to parse DT node %s\n", np->name); in rza2_dt_node_to_map()
450 return -EINVAL; in rza2_set_mux()
454 return -EINVAL; in rza2_set_mux()
456 psel_val = func->data; in rza2_set_mux()
458 for (i = 0; i < grp->grp.npins; ++i) { in rza2_set_mux()
459 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n", in rza2_set_mux()
460 port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])], in rza2_set_mux()
461 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]), in rza2_set_mux()
464 priv->base, in rza2_set_mux()
465 RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]), in rza2_set_mux()
466 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]), in rza2_set_mux()
486 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in rza2_pinctrl_probe()
488 return -ENOMEM; in rza2_pinctrl_probe()
490 priv->dev = &pdev->dev; in rza2_pinctrl_probe()
492 priv->base = devm_platform_ioremap_resource(pdev, 0); in rza2_pinctrl_probe()
493 if (IS_ERR(priv->base)) in rza2_pinctrl_probe()
494 return PTR_ERR(priv->base); in rza2_pinctrl_probe()
496 mutex_init(&priv->mutex); in rza2_pinctrl_probe()
500 priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * in rza2_pinctrl_probe()
503 priv->desc.name = DRIVER_NAME; in rza2_pinctrl_probe()
504 priv->desc.pctlops = &rza2_pinctrl_ops; in rza2_pinctrl_probe()
505 priv->desc.pmxops = &rza2_pinmux_ops; in rza2_pinctrl_probe()
506 priv->desc.owner = THIS_MODULE; in rza2_pinctrl_probe()
512 dev_info(&pdev->dev, "Registered ports P0 - P%c\n", in rza2_pinctrl_probe()
513 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]); in rza2_pinctrl_probe()
519 { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
538 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");