Lines Matching +full:soc +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/soc/qcom/irq.h>
33 #include "../pinctrl-utils.h"
35 #include "pinctrl-msm.h"
42 * struct msm_pinctrl - state for a pinctrl-msm device
57 * @soc: Reference to soc_data of platform specific data.
79 const struct msm_pinctrl_soc_data *soc; member
88 return readl(pctrl->regs[g->tile] + g->name##_reg); \
93 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
105 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
114 return pctrl->soc->ngroups; in msm_get_groups_count()
122 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
132 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
133 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
148 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
150 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
157 return pctrl->soc->nfunctions; in msm_get_functions_count()
165 return pctrl->soc->functions[function].name; in msm_get_function_name()
175 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
176 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
185 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
186 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
188 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
189 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
195 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
196 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
198 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
199 if (g->funcs[i] == function) in msm_pinmux_set_mux()
203 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
204 return -EINVAL; in msm_pinmux_set_mux()
217 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
220 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
230 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
231 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
234 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
235 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
236 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
238 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
239 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
244 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
245 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
248 val |= i << g->mux_bit; in msm_pinmux_set_mux()
250 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
251 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
256 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
259 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
264 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
280 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
283 if (!g->nfuncs) in msm_pinmux_request_gpio()
286 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
309 *bit = g->pull_bit; in msm_config_reg()
311 if (g->i2c_pull_bit) in msm_config_reg()
312 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
315 *bit = g->od_bit; in msm_config_reg()
319 *bit = g->drv_bit; in msm_config_reg()
325 *bit = g->oe_bit; in msm_config_reg()
329 return -ENOTSUPP; in msm_config_reg()
361 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
362 return -EINVAL; in msm_config_group_get()
364 g = &pctrl->soc->groups[group]; in msm_config_group_get()
377 return -EINVAL; in msm_config_group_get()
382 return -EINVAL; in msm_config_group_get()
386 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
387 return -ENOTSUPP; in msm_config_group_get()
390 return -EINVAL; in msm_config_group_get()
394 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
396 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
401 return -EINVAL; in msm_config_group_get()
404 /* Pin is not open-drain */ in msm_config_group_get()
406 return -EINVAL; in msm_config_group_get()
415 return -EINVAL; in msm_config_group_get()
418 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
422 return -EINVAL; in msm_config_group_get()
425 return -ENOTSUPP; in msm_config_group_get()
449 g = &pctrl->soc->groups[group]; in msm_config_group_set()
468 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
469 return -ENOTSUPP; in msm_config_group_set()
474 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
476 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
477 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
487 arg = -1; in msm_config_group_set()
489 arg = (arg / 2) - 1; in msm_config_group_set()
493 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
496 val |= BIT(g->out_bit); in msm_config_group_set()
498 val &= ~BIT(g->out_bit); in msm_config_group_set()
500 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
508 * actually be a no-op. in msm_config_group_set()
511 * the pin's ability to drive output" but what we do in msm_config_group_set()
517 * can be enabled/disabled. It's always on. in msm_config_group_set()
520 * no-op. However, for historical reasons and to in msm_config_group_set()
526 * that "input-enable" and "input-disable" in a device in msm_config_group_set()
537 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
539 return -EINVAL; in msm_config_group_set()
542 /* Range-check user-supplied value */ in msm_config_group_set()
544 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
545 return -EINVAL; in msm_config_group_set()
548 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
553 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
572 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
574 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
577 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
580 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
592 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
594 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
598 val |= BIT(g->out_bit); in msm_gpio_direction_output()
600 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
604 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
607 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
618 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
622 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
632 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
635 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
645 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
647 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
651 val |= BIT(g->out_bit); in msm_gpio_set()
653 val &= ~BIT(g->out_bit); in msm_gpio_set()
656 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
661 static void msm_gpio_dbg_show_one(struct seq_file *s, in msm_gpio_dbg_show_one() argument
693 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
697 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
698 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
699 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
700 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
702 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
703 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
706 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
708 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
711 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
715 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
716 seq_printf(s, " %-4s func%d", str_high_low(val), func); in msm_gpio_dbg_show_one()
717 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); in msm_gpio_dbg_show_one()
718 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
719 seq_printf(s, " %s", pulls_no_keeper[pull]); in msm_gpio_dbg_show_one()
721 seq_printf(s, " %s", pulls_keeper[pull]); in msm_gpio_dbg_show_one()
722 seq_puts(s, "\n"); in msm_gpio_dbg_show_one()
725 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) in msm_gpio_dbg_show() argument
727 unsigned gpio = chip->base; in msm_gpio_dbg_show()
730 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
731 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); in msm_gpio_dbg_show()
745 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
748 /* Remove driver-provided reserved GPIOs from valid_mask */ in msm_gpio_init_valid_mask()
752 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
753 return -EINVAL; in msm_gpio_init_valid_mask()
762 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
767 return -EINVAL; in msm_gpio_init_valid_mask()
771 return -ENOMEM; in msm_gpio_init_valid_mask()
773 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
775 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
799 /* For dual-edge interrupts in software, since some hardware has no
803 * settings of both-edge irq lines to try and catch the next edge.
806 * - the status bit goes high, indicating that an edge was caught, or
807 * - the input value of the gpio doesn't change during the attempt.
812 * The do-loop tries to sledge-hammer closed the timing hole between
813 * the initial value-read and the polarity-write - if the line value changes
817 * Algorithm comes from Google's msmgpio driver.
828 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
831 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
834 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
838 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
839 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
851 if (d->parent_data) in msm_gpio_irq_mask()
854 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
857 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
859 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
866 * an irq that it's configured for (either edge for edge type or level in msm_gpio_irq_mask()
867 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
869 * status bit is set. There's a bug though, the edge detection logic in msm_gpio_irq_mask()
876 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
880 * while it's masked. in msm_gpio_irq_mask()
883 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
885 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
888 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
890 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
901 if (d->parent_data) in msm_gpio_irq_unmask()
904 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
907 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
909 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
912 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
913 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
916 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
918 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
926 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
928 if (d->parent_data) in msm_gpio_irq_enable()
931 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
940 if (d->parent_data) in msm_gpio_irq_disable()
943 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
946 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
950 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
955 * different due to what's easy to do with our parent, but in principle it's
962 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
968 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
981 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
991 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
992 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
1002 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1003 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1008 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1010 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1014 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1017 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1022 d = d->parent_data; in msm_gpio_irq_eoi()
1025 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
1035 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1036 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1049 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1055 if (d->parent_data) in msm_gpio_irq_set_type()
1058 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1059 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1064 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1066 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1071 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1072 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1074 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1080 if (g->intr_target_width) in msm_gpio_irq_set_type()
1081 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1083 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1084 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1088 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1089 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1093 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1095 d->hwirq); in msm_gpio_irq_set_type()
1098 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1099 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1109 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1110 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1111 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1112 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1115 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1116 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1119 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1120 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1123 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1124 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1129 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1132 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1133 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1134 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1137 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1138 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1141 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1144 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1145 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1150 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1162 * also still have a non-matching interrupt latched, so clear whenever in msm_gpio_irq_set_type()
1168 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1171 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1192 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1195 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1202 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres()
1206 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1207 return -ENODEV; in msm_gpio_irq_reqres()
1209 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1212 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1214 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1215 dev_err(gc->parent, in msm_gpio_irq_reqres()
1217 d->hwirq); in msm_gpio_irq_reqres()
1218 ret = -EINVAL; in msm_gpio_irq_reqres()
1223 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1227 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1234 * While the name implies only the wakeup event, it's also required for in msm_gpio_irq_reqres()
1237 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1240 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1243 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_reqres()
1244 intr_cfg |= BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_reqres()
1248 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1253 module_put(gc->owner); in msm_gpio_irq_reqres()
1261 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres()
1265 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1268 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1271 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { in msm_gpio_irq_relres()
1272 intr_cfg &= ~BIT(g->intr_wakeup_enable_bit); in msm_gpio_irq_relres()
1276 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1279 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1280 module_put(gc->owner); in msm_gpio_irq_relres()
1289 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1292 return -EINVAL; in msm_gpio_irq_set_affinity()
1300 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1303 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1319 * Each pin has it's own IRQ status register, so use in msm_gpio_irq_handler()
1322 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1323 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1325 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1326 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1351 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1352 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1353 if (map->gpio == child) { in msm_gpio_wakeirq()
1354 *parent = map->wakeirq; in msm_gpio_wakeirq()
1364 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1367 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1395 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1400 return -EINVAL; in msm_gpio_init()
1402 chip = &pctrl->chip; in msm_gpio_init()
1403 chip->base = -1; in msm_gpio_init()
1404 chip->ngpio = ngpio; in msm_gpio_init()
1405 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1406 chip->parent = pctrl->dev; in msm_gpio_init()
1407 chip->owner = THIS_MODULE; in msm_gpio_init()
1409 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1411 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1413 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1416 if (!chip->irq.parent_domain) in msm_gpio_init()
1417 return -EPROBE_DEFER; in msm_gpio_init()
1418 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1420 * Let's skip handling the GPIOs, if the parent irqchip in msm_gpio_init()
1423 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1424 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1425 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1426 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1430 girq = &chip->irq; in msm_gpio_init()
1432 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1433 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1434 girq->num_parents = 1; in msm_gpio_init()
1435 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1437 if (!girq->parents) in msm_gpio_init()
1438 return -ENOMEM; in msm_gpio_init()
1439 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1440 girq->handler = handle_bad_irq; in msm_gpio_init()
1441 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1443 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1445 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1450 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1451 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1456 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1459 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1460 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1461 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1463 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1464 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1474 struct msm_pinctrl *pctrl = data->cb_data; in msm_ps_hold_restart()
1476 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1495 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1497 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1499 if (devm_register_sys_off_handler(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1504 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1516 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1523 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1539 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1541 return -ENOMEM; in msm_pinctrl_probe()
1543 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1544 pctrl->soc = soc_data; in msm_pinctrl_probe()
1545 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1546 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1547 pctrl->dev->of_node, in msm_pinctrl_probe()
1548 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1550 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1552 if (soc_data->tiles) { in msm_pinctrl_probe()
1553 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1555 soc_data->tiles[i]); in msm_pinctrl_probe()
1556 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1557 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1558 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1561 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1562 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1563 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1565 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1570 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1571 if (pctrl->irq < 0) in msm_pinctrl_probe()
1572 return pctrl->irq; in msm_pinctrl_probe()
1574 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1575 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1576 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1577 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1578 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1579 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1580 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1582 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1583 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1584 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1585 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1594 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1604 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()