drivers/pinctrl/pinctrl-ingenic.c

1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
82 #define GPIO_PULL_DOWN				2
177 		(!(enabled_socs & GENMASK(version - 1, 0))  in is_soc_or_above()
178 		 || jzpc->info->version >= version);  in is_soc_or_above()
221 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
224 	INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
225 	INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
226 	INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
227 	INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
228 	INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
229 	INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
230 	INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
231 	INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
232 	INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
233 	INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
234 	INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
235 	INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
236 	INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
237 	INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
238 	INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
239 	INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
243 	INGENIC_PIN_GROUP("i2s-mclk-out", jz4730_i2s_mclk, 1),
244 	INGENIC_PIN_GROUP("i2s-acreset", jz4730_i2s_acreset, 1),
245 	INGENIC_PIN_GROUP("i2s-data", jz4730_i2s_data, 1),
246 	INGENIC_PIN_GROUP("i2s-master", jz4730_i2s_clock, 1),
247 	INGENIC_PIN_GROUP("i2s-slave", jz4730_i2s_clock, 2),
250 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
251 static const char *jz4730_uart0_groups[] = { "uart0-data", };
252 static const char *jz4730_uart1_groups[] = { "uart1-data", };
253 static const char *jz4730_uart2_groups[] = { "uart2-data", };
254 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
256 	"lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
259 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
264 static const char *jz4730_i2s_groups[] = { "i2s-data", "i2s-master", "i2s-slave", };
330 	INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
331 	INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
332 	INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
333 	INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
334 	INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
335 	INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
336 	INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
337 	INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
338 	INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
339 	INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
340 	INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
341 	INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
342 	INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
343 	INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
344 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
355 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
356 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
357 static const char *jz4740_uart1_groups[] = { "uart1-data", };
359 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
362 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
433 	INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
434 	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
436 	INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
437 	INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
438 	INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
439 	INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
440 	INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
441 	INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
442 	INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
443 	INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
444 	INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
445 	INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
446 	INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
447 	INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
448 	INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
449 	INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
450 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
459 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
460 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
461 static const char *jz4725b_uart_groups[] = { "uart-data", };
463 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
464 	"lcd-special", "lcd-generic",
467 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
468 	"nand-cle-ale", "nand-fre-fwe",
552 	INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
553 	INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
554 	INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
555 	INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
556 	INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
557 	INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
558 	INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
559 	INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
560 	INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
561 	INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
562 	INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
563 	INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
564 	INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
565 	INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
566 	INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
567 	INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
568 	INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
569 	INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
570 	INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
571 	INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
572 	INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
573 	INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
574 	INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
575 	INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
576 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
585 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
586 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
587 static const char *jz4750_uart2_groups[] = { "uart2-data", };
588 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
590 	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
592 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
593 static const char *jz4750_i2c_groups[] = { "i2c-data", };
594 static const char *jz4750_cim_groups[] = { "cim-data", };
596 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
597 	"lcd-special", "lcd-generic",
600 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
696 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
701 	INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
702 	INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
703 	INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
704 	INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
705 	INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
706 	INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
707 	INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
708 	INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
709 	INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
710 	INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
711 	INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
712 	INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
713 	INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
714 	INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
715 	INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
716 	INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
717 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
719 	INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
721 	INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
722 	INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
723 	INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
724 	INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
725 	INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
726 	INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
727 	INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
728 	INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
730 	INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
731 	INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
732 	INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
733 	INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
734 	INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
735 	INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
736 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
745 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
746 static const char *jz4755_uart1_groups[] = { "uart1-data", };
747 static const char *jz4755_uart2_groups[] = { "uart2-data", };
749 	"ssi-dt-b", "ssi-dt-f",
750 	"ssi-dr-b", "ssi-dr-f",
751 	"ssi-clk-b", "ssi-clk-f",
752 	"ssi-gpc-b", "ssi-gpc-f",
753 	"ssi-ce0-b", "ssi-ce0-f",
754 	"ssi-ce1-b", "ssi-ce1-f",
756 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
757 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
758 static const char *jz4755_i2c_groups[] = { "i2c-data", };
759 static const char *jz4755_cim_groups[] = { "cim-data", };
761 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
762 	"lcd-special", "lcd-generic",
765 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
940 	INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
941 	INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
942 	INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
943 	INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
944 	INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
945 	INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
946 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
948 	INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
949 	INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
950 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
951 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
952 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
953 	INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
954 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
955 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
956 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
957 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
958 	INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
959 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
960 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
961 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
962 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
963 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
964 	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
965 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
966 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
967 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
968 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
969 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
970 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
971 	INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
972 	INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
973 	INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
974 	INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
975 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
976 	INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
977 	INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
978 	INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
979 	INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
980 	INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
981 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
982 	INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
983 	INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
984 	INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
985 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
986 	INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
987 	INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
988 	INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
989 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
990 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
991 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
992 	INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
993 	INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
994 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
995 	INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
996 	INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
997 	INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
998 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
999 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
1000 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
1001 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
1003 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
1004 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
1005 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
1006 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
1007 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
1008 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
1009 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
1010 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
1011 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
1012 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
1013 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
1014 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
1015 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
1016 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
1017 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
1018 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
1019 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
1020 	INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
1021 	INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
1022 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
1023 	INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
1024 	INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
1025 	INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
1026 	INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
1027 	INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
1028 	INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
1029 	INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
1030 	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
1031 	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
1032 	INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
1033 	INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
1034 	INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
1035 	INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
1036 	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
1037 	INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
1038 	INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
1047 	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1050 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1051 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1052 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1053 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1055 	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1056 	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1057 	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1058 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1059 	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1060 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1063 	"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1064 	"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1065 	"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1066 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1067 	"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1068 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1071 	"mmc0-1bit-a", "mmc0-4bit-a",
1072 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1075 	"mmc1-1bit-d", "mmc1-4bit-d",
1076 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1079 	"mmc2-1bit-b", "mmc2-4bit-b",
1080 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1083 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1084 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1086 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1087 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1088 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1089 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1090 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1091 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1092 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1093 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1094 static const char *jz4760_cim_groups[] = { "cim-data", };
1096 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1097 	"lcd-special", "lcd-generic",
1107 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1120 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
1121 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
1122 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
1123 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
1124 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
1125 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
1285 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1286 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1287 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1288 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1289 	INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1290 	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1291 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1293 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1294 	INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1295 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1296 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1297 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1298 	INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1299 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1300 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1301 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1302 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1303 	INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1304 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1305 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1306 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1307 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1308 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1309 	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1310 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1311 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1312 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1313 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1314 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1315 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1316 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1317 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1318 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1319 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1320 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1321 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1322 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1323 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1324 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1325 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1326 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1327 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1328 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1329 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1330 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1331 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1332 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1333 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1334 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1336 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1337 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1338 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1339 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1340 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1341 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1342 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1343 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1344 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1345 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1346 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1347 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1348 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1349 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1350 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1351 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1352 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1353 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1354 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1355 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1356 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1357 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1358 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1359 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1360 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1361 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1362 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1363 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1364 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1365 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1366 	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1367 	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1368 	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1369 	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1370 	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1371 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1372 	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1373 	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1382 	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1383 	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1384 	INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1387 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1388 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1389 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1390 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1392 	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1393 	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1394 	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1395 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1396 	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1397 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1400 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1401 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1402 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1403 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1404 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1405 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1408 	"mmc0-1bit-a", "mmc0-4bit-a",
1409 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1412 	"mmc1-1bit-d", "mmc1-4bit-d",
1413 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1416 	"mmc2-1bit-b", "mmc2-4bit-b",
1417 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1420 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1421 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1423 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1424 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1425 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1426 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1427 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1428 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1429 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1430 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1431 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1432 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1434 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1435 	"lcd-special", "lcd-generic",
1445 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1458 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1459 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1460 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1461 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1462 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1463 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1604 	INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1605 	INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1606 	INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1607 	INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1608 	INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1609 	INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1610 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1612 	INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1613 	INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1614 	INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1615 	INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1616 	INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1617 	INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1618 	INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1619 	INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1620 	INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1621 	INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1622 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1623 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1624 	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1625 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1626 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1627 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1628 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1629 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1630 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1631 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1632 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1633 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1634 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1635 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1636 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1637 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1638 	INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1639 	INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1640 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1641 	INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1642 	INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1643 	INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1644 	INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1645 	INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1646 	INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1647 	INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1648 	INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1649 	INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1650 	INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1651 	INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1653 	INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1654 	INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1655 	INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1656 	INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1657 	INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1658 	INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1659 	INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1664 	INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1665 	INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1667 	INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1669 	INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1671 	INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1674 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1675 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1676 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1677 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1679 	"ssi-dt-a", "ssi-dt-d",
1680 	"ssi-dr-a", "ssi-dr-d",
1681 	"ssi-clk-a", "ssi-clk-d",
1682 	"ssi-gpc",
1683 	"ssi-ce0-a", "ssi-ce0-d",
1684 	"ssi-ce1",
1687 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1688 	"mmc0-1bit-e", "mmc0-4bit-e",
1691 	"mmc1-1bit-d", "mmc1-4bit-d",
1692 	"mmc1-1bit-e", "mmc1-4bit-e",
1695 	"mmc2-1bit-b", "mmc2-4bit-b",
1696 	"mmc2-1bit-e", "mmc2-4bit-e",
1699 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1700 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1702 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1703 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1704 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1705 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1706 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1707 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1709 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1712 static const char *jz4775_cim_groups[] = { "cim-data", };
1714 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1715 	"lcd-special", "lcd-generic",
1722 	"mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1724 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1736 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
1737 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
1738 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
1825 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1826 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1827 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1828 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1829 	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1830 	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1831 	INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1833 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1834 	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1835 	INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1836 	INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1837 	INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1838 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1839 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1840 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1841 	INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1842 	INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1843 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1844 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1845 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1846 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1847 	INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1848 	INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1849 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1850 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1851 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1852 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1853 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1854 	INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1855 	INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1856 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1857 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1858 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1859 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1860 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1861 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1862 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1863 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1864 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1865 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1866 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1867 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1868 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1869 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1870 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1871 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1872 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1873 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1874 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1875 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1876 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1877 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1878 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1879 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1880 	INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1882 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1883 	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1884 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1885 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1886 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1887 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1888 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1889 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1890 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1891 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1892 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1893 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1894 	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1895 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1896 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1897 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1898 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1899 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1900 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1901 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1902 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1903 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1904 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1905 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1906 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1907 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1908 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1909 	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1910 	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1911 	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1912 	INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1913 	INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1914 	INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1916 	INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1917 	INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1919 	INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1920 	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1921 	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1922 	INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1923 	INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1924 	INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1925 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1926 	INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1927 	INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1938 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1939 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1941 	"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1942 	"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1943 	"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1944 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1945 	"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1946 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1949 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1950 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1951 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1952 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1953 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1954 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1957 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1958 	"mmc0-1bit-e", "mmc0-4bit-e",
1961 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1964 	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1967 	"nemc-data", "nemc-cle-ale", "nemc-addr",
1968 	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1970 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1971 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1973 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1976 static const char *jz4780_cim_groups[] = { "cim-data", };
1977 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1991 	INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1992 	INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1993 	INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1994 	INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1995 	INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1996 	INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
2014 	INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
2113 	INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2114 	INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2115 	INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2116 	INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2117 	INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2118 	INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2119 	INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2120 	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2121 	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2122 	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2123 	INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2124 	INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2125 	INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2126 	INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2127 	INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2128 	INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2129 	INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2130 	INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2131 	INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2132 	INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2133 	INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2134 	INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2135 	INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2136 	INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2137 	INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2138 	INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2139 	INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2140 	INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2141 	INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2142 	INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2143 	INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2144 	INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2145 	INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2146 	INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2147 	INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2148 	INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2149 	INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2150 	INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2151 	INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2152 	INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2153 	INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2154 	INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2155 	INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2156 	INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2157 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2158 	INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2159 	INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2160 	INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2161 	INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2162 	INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2163 	INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2167 	INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2172 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2174 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2176 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2177 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2179 	"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2180 	"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2181 	"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2182 	"ssi-gpc-a-20", "ssi-gpc-a-31",
2183 	"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2184 	"ssi-ce1-a-21", "ssi-ce1-a-30",
2187 	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2190 	"mmc1-1bit", "mmc1-4bit",
2193 	"emc-8bit-data", "emc-16bit-data",
2194 	"emc-addr", "emc-rd-we", "emc-wait",
2196 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2197 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2198 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2199 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2200 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2202 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2204 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2205 static const char *x1000_cim_groups[] = { "cim-data", };
2206 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2222 	INGENIC_PIN_FUNCTION("emc", x1000_emc),
2223 	INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
2224 	INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
2241 	regmap_reg_range(0x000, 0x400 - 4),
2242 	regmap_reg_range(0x700, 0x800 - 4),
2294 	INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2295 	INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2296 	INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2297 	INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2298 	INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2299 	INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2300 	INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2301 	INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2302 	INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2303 	INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2304 	INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2305 	INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2306 	INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2307 	INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2308 	INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2309 	INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2310 	INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2311 	INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2312 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2313 	INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2314 	INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2315 	INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2316 	INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2320 	INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2324 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2326 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
2328 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2329 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2330 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2331 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2332 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2334 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2336 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2337 static const char *x1500_cim_groups[] = { "cim-data", };
2463 static int x1600_sfc_funcs[] = { 0, 0, 0, 0, 0, 0, 2, };
2466 	INGENIC_PIN_GROUP("uart0-data", x1600_uart0_data, 0),
2467 	INGENIC_PIN_GROUP("uart0-hwflow", x1600_uart0_hwflow, 0),
2468 	INGENIC_PIN_GROUP("uart1-data", x1600_uart1_data, 1),
2469 	INGENIC_PIN_GROUP("uart1-hwflow", x1600_uart1_hwflow, 1),
2470 	INGENIC_PIN_GROUP("uart2-data-a", x1600_uart2_data_a, 2),
2471 	INGENIC_PIN_GROUP("uart2-data-b", x1600_uart2_data_b, 1),
2472 	INGENIC_PIN_GROUP("uart3-data-b", x1600_uart3_data_b, 0),
2473 	INGENIC_PIN_GROUP("uart3-data-d", x1600_uart3_data_d, 2),
2475 	INGENIC_PIN_GROUP("ssi-dt-a", x1600_ssi_dt_a, 0),
2476 	INGENIC_PIN_GROUP("ssi-dt-b", x1600_ssi_dt_b, 1),
2477 	INGENIC_PIN_GROUP("ssi-dr-a", x1600_ssi_dr_a, 0),
2478 	INGENIC_PIN_GROUP("ssi-dr-b", x1600_ssi_dr_b, 1),
2479 	INGENIC_PIN_GROUP("ssi-clk-a", x1600_ssi_clk_a, 0),
2480 	INGENIC_PIN_GROUP("ssi-clk-b", x1600_ssi_clk_b, 1),
2481 	INGENIC_PIN_GROUP("ssi-ce0-a", x1600_ssi_ce0_a, 0),
2482 	INGENIC_PIN_GROUP("ssi-ce0-b", x1600_ssi_ce0_b, 1),
2483 	INGENIC_PIN_GROUP("ssi-ce1-a", x1600_ssi_ce1_a, 2),
2484 	INGENIC_PIN_GROUP("ssi-ce1-b", x1600_ssi_ce1_b, 1),
2485 	INGENIC_PIN_GROUP("mmc0-1bit-b", x1600_mmc0_1bit_b, 0),
2486 	INGENIC_PIN_GROUP("mmc0-4bit-b", x1600_mmc0_4bit_b, 0),
2487 	INGENIC_PIN_GROUP("mmc0-1bit-c", x1600_mmc0_1bit_c, 1),
2488 	INGENIC_PIN_GROUP("mmc0-4bit-c", x1600_mmc0_4bit_c, 1),
2489 	INGENIC_PIN_GROUP("mmc1-1bit", x1600_mmc1_1bit, 0),
2490 	INGENIC_PIN_GROUP("mmc1-4bit", x1600_mmc1_4bit, 0),
2491 	INGENIC_PIN_GROUP("i2c0-data-a", x1600_i2c0_a, 2),
2492 	INGENIC_PIN_GROUP("i2c0-data-b", x1600_i2c0_b, 0),
2493 	INGENIC_PIN_GROUP("i2c1-data-b-15", x1600_i2c1_b_15, 2),
2494 	INGENIC_PIN_GROUP("i2c1-data-b-19", x1600_i2c1_b_19, 0),
2495 	INGENIC_PIN_GROUP("i2s-data-tx", x1600_i2s_data_tx, 0),
2496 	INGENIC_PIN_GROUP("i2s-data-rx", x1600_i2s_data_rx, 0),
2497 	INGENIC_PIN_GROUP("i2s-clk-rx", x1600_i2s_clk_rx, 0),
2498 	INGENIC_PIN_GROUP("i2s-clk-tx", x1600_i2s_clk_tx, 0),
2499 	INGENIC_PIN_GROUP("i2s-sysclk", x1600_i2s_sysclk, 0),
2500 	INGENIC_PIN_GROUP("cim-data", x1600_cim, 2),
2501 	INGENIC_PIN_GROUP("slcd-8bit", x1600_slcd_8bit, 1),
2502 	INGENIC_PIN_GROUP("slcd-16bit", x1600_slcd_16bit, 1),
2503 	INGENIC_PIN_GROUP("lcd-16bit", x1600_lcd_16bit, 0),
2504 	INGENIC_PIN_GROUP("lcd-18bit", x1600_lcd_18bit, 0),
2505 	INGENIC_PIN_GROUP("lcd-24bit", x1600_lcd_24bit, 0),
2511 	INGENIC_PIN_GROUP("pwm5-b", x1600_pwm_pwm5_b, 2),
2512 	INGENIC_PIN_GROUP("pwm5-c", x1600_pwm_pwm5_c, 1),
2513 	INGENIC_PIN_GROUP("pwm6-b9", x1600_pwm_pwm6_b9, 1),
2514 	INGENIC_PIN_GROUP("pwm6-b20", x1600_pwm_pwm6_b20, 2),
2515 	INGENIC_PIN_GROUP("pwm7-b10", x1600_pwm_pwm7_b10, 1),
2516 	INGENIC_PIN_GROUP("pwm7-b21", x1600_pwm_pwm7_b21, 2),
2520 static const char * const x1600_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2521 static const char * const x1600_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2522 static const char * const x1600_uart2_groups[] = { "uart2-data-a", "uart2-data-b", };
2523 static const char * const x1600_uart3_groups[] = { "uart3-data-b", "uart3-data-d", };
2528 	"ssi-dt-a", "ssi-dt-b",
2529 	"ssi-dr-a", "ssi-dr-b",
2530 	"ssi-clk-a", "ssi-clk-b",
2531 	"ssi-ce0-a", "ssi-ce0-b",
2532 	"ssi-ce1-a", "ssi-ce1-b",
2535 static const char * const x1600_mmc0_groups[] = { "mmc0-1bit-b", "mmc0-4bit-b",
2536 	"mmc0-1bit-c", "mmc0-4bit-c",
2539 static const char * const x1600_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2541 static const char * const x1600_i2c0_groups[] = { "i2c0-data-a", "i2c0-data-b", };
2542 static const char * const x1600_i2c1_groups[] = { "i2c1-data-b-15", "i2c1-data-b-19", };
2545 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-rx", "i2s-clk-tx", "i2s-sysclk",
2548 static const char * const x1600_cim_groups[] = { "cim-data", };
2550 static const char * const x1600_lcd_groups[] = { "slcd-8bit", "slcd-16bit",
2551 	"lcd-16bit", "lcd-18bit", "lcd-24bit", "lcd-no-pins",
2559 static const char * const x1600_pwm5_groups[] = { "pwm5-b", "pwm5-c", };
2560 static const char * const x1600_pwm6_groups[] = { "pwm6-b9", "pwm6-b20", };
2561 static const char * const x1600_pwm7_groups[] = { "pwm7-b10", "pwm7-b21", };
2685 	INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2686 	INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2687 	INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2688 	INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2689 	INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2690 	INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2691 	INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2692 	INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2693 	INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2694 	INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2695 	INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2696 	INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2697 	INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2698 	INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2699 	INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2700 	INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2701 	INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2702 	INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2703 	INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2704 	INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2705 	INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2706 	INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2707 	INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2708 	INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2709 	INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2710 	INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2711 	INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2712 	INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2713 	INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2714 	INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2715 	INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2716 	INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2717 	INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2718 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2719 	INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2720 	INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2721 	INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2722 	INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2723 	INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2724 	INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2725 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2726 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2727 	INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2728 	INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2729 	INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2730 	INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2731 	INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2732 	INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2733 	INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2734 	INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2735 	INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2736 	INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2737 	INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2738 	INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2739 	INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2740 	INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2741 	INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2742 	INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2746 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2747 static const char *x1830_uart1_groups[] = { "uart1-data", };
2748 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2750 	"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2753 	"ssi1-dt-c", "ssi1-dt-d",
2754 	"ssi1-dr-c", "ssi1-dr-d",
2755 	"ssi1-clk-c", "ssi1-clk-d",
2756 	"ssi1-gpc-c", "ssi1-gpc-d",
2757 	"ssi1-ce0-c", "ssi1-ce0-d",
2758 	"ssi1-ce1-c", "ssi1-ce1-d",
2760 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2761 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2762 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2763 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2764 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2766 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2768 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2770 	"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2772 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2773 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2774 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2775 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2776 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2777 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2778 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2779 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2808 	regmap_reg_range(0x0000, 0x4000 - 4),
2809 	regmap_reg_range(0x7000, 0x8000 - 4),
3003 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
3006 	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3007 	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3008 	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3009 	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3010 	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3011 	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3012 	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3013 	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3014 	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3015 	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3016 	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3017 	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3018 	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3019 	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3020 	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3021 	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3022 	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3023 	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3024 	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3025 	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3026 	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3027 	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3028 	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3029 	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3030 	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3031 	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3032 	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3033 	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3034 	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3035 	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3036 	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3037 	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3038 	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3039 	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3040 	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3041 	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3042 	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3043 	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3044 	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3045 	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3046 	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3047 	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3048 	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3049 	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3050 	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3051 	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3052 	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3053 	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3054 	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3055 	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3056 	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3057 	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3058 	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3059 	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3060 	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3061 	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3062 	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3063 	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3064 	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3065 	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3066 	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3067 	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3068 	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3069 	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3070 	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3071 	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3072 	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3073 	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3074 	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3075 	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3076 	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3077 	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3078 	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3079 	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3080 	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3081 	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3082 	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3083 	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3084 	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3085 	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3086 	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3087 	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3088 	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3089 	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3090 	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3091 	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3092 	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3093 	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3094 	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3095 	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3096 	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3097 	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3098 	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3099 	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3100 	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3101 	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3102 	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3104 	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3105 	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3106 	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3107 	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3108 	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3109 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3110 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3111 	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3112 	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3113 	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3114 	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3115 	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3116 	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3117 	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3118 	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3119 	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3120 	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3121 	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3122 	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3123 	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3124 	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3125 	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3126 	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3135 	INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
3136 	INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
3137 	INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
3138 	INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
3139 	INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
3142 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
3143 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
3144 static const char *x2000_uart2_groups[] = { "uart2-data", };
3146 	"uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
3149 	"uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
3151 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
3152 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
3153 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
3154 static const char *x2000_uart8_groups[] = { "uart8-data", };
3155 static const char *x2000_uart9_groups[] = { "uart9-data", };
3157 	"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
3158 	"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
3161 	"ssi0-dt-b", "ssi0-dt-d",
3162 	"ssi0-dr-b", "ssi0-dr-d",
3163 	"ssi0-clk-b", "ssi0-clk-d",
3164 	"ssi0-ce-b", "ssi0-ce-d",
3167 	"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
3168 	"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
3169 	"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
3170 	"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
3172 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
3173 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
3174 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
3176 	"emc-8bit-data", "emc-16bit-data",
3177 	"emc-addr", "emc-rd-we", "emc-wait",
3179 static const char *x2000_cs1_groups[] = { "emc-cs1", };
3180 static const char *x2000_cs2_groups[] = { "emc-cs2", };
3181 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
3182 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
3183 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
3184 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
3185 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
3186 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
3188 	"i2s1-data-tx", "i2s1-data-rx",
3189 	"i2s1-clk-tx", "i2s1-clk-rx",
3190 	"i2s1-sysclk-tx", "i2s1-sysclk-rx",
3193 	"i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
3194 	"i2s2-clk-rx", "i2s2-sysclk-rx",
3197 	"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
3198 	"i2s3-clk-tx", "i2s3-sysclk-tx",
3201 	"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
3203 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
3205 	"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
3206 	"lcd-slcd-8bit", "lcd-slcd-16bit",
3208 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
3209 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
3210 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
3211 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
3212 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
3213 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
3214 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
3215 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
3224 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
3225 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
3226 static const char *x2000_otg_groups[] = { "otg-vbus", };
3245 	INGENIC_PIN_FUNCTION("emc", x2000_emc),
3246 	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3247 	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3282 	regmap_reg_range(0x000, 0x500 - 4),
3283 	regmap_reg_range(0x700, 0x800 - 4),
3318 	INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
3319 	INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
3320 	INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3321 	INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3322 	INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3323 	INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3324 	INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3325 	INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3326 	INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3327 	INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3328 	INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3329 	INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3330 	INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3331 	INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3332 	INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3333 	INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3334 	INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3335 	INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3336 	INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3337 	INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3338 	INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3339 	INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3340 	INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3341 	INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3342 	INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3343 	INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3344 	INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3345 	INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3346 	INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3347 	INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3348 	INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3349 	INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3350 	INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3351 	INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3352 	INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3353 	INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3354 	INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3355 	INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3356 	INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3357 	INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3358 	INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3359 	INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3360 	INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3361 	INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3362 	INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3363 	INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3364 	INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3365 	INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3366 	INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3367 	INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3368 	INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3369 	INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3370 	INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3371 	INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3372 	INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3373 	INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3374 	INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3375 	INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3376 	INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3377 	INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3378 	INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3379 	INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3380 	INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3381 	INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3382 	INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3383 	INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3384 	INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3385 	INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3386 	INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3387 	INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3388 	INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3389 	INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3390 	INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3391 	INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3392 	INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3393 	INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3394 	INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3395 	INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3396 	INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3397 	INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3398 	INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3399 	INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3400 	INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3401 	INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3402 	INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3403 	INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3404 	INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3405 	INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3406 	INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3407 	INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3408 	INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3409 	INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3410 	INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3411 	INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3412 	INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3413 	INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3414 	INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3416 	INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3417 	INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3418 	INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3419 	INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3420 	INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3421 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3422 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3423 	INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3424 	INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3425 	INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3426 	INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3427 	INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3428 	INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3429 	INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3430 	INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3431 	INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3432 	INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3433 	INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3434 	INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3435 	INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3436 	INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3437 	INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3438 	INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3469 	INGENIC_PIN_FUNCTION("emc", x2000_emc),
3470 	INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3471 	INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3520 	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);  in ingenic_gpio_read_reg()
3528 	if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {  in ingenic_gpio_set_bit()
3529 		regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,  in ingenic_gpio_set_bit()
3539 	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));  in ingenic_gpio_set_bit()
3550 	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(  in ingenic_gpio_shadow_set_bit()
3551 			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));  in ingenic_gpio_shadow_set_bit()
3556 	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(  in ingenic_gpio_shadow_set_bit_load()
3557 			jzgc->jzpc->info->reg_offset),  in ingenic_gpio_shadow_set_bit_load()
3558 			jzgc->gc.base / PINS_PER_GPIO_CHIP);  in ingenic_gpio_shadow_set_bit_load()
3565 	 * JZ4730 function and IRQ registers support two-bits-per-pin  in jz4730_gpio_set_bits()
3570 	unsigned int mask = GENMASK(1, 0) << idx * 2;  in jz4730_gpio_set_bits()
3572 	regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));  in jz4730_gpio_set_bits()
3586 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_set_value()
3588 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_set_value()
3623 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {  in irq_set_type()
3626 	} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {  in irq_set_type()
3636 	if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in irq_set_type()
3641 	} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {  in irq_set_type()
3657 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_mask()
3669 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_unmask()
3683 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_enable()
3685 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_enable()
3701 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_disable()
3703 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_disable()
3719 	    !is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in ingenic_gpio_irq_ack()
3731 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_ack()
3733 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_ack()
3759 	if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {  in ingenic_gpio_irq_set_type()
3762 		 * best we can do is to set up a single-edge interrupt and then  in ingenic_gpio_irq_set_type()
3779 	return irq_set_irq_wake(jzgc->irq, on);  in ingenic_gpio_irq_set_wake()
3786 	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);  in ingenic_gpio_irq_handler()
3791 	if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))  in ingenic_gpio_irq_handler()
3793 	else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))  in ingenic_gpio_irq_handler()
3799 		generic_handle_domain_irq(gc->irq.domain, i);  in ingenic_gpio_irq_handler()
3833 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3836 			regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3840 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3843 			regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
3853 	regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +  in ingenic_shadow_config_pin()
3860 	regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),  in ingenic_shadow_config_pin_load()
3868 	 * JZ4730 function and IRQ registers support two-bits-per-pin  in jz4730_config_pin_function()
3872 	unsigned int mask = GENMASK(1, 0) << idx * 2;  in jz4730_config_pin_function()
3876 	regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,  in jz4730_config_pin_function()
3877 			mask, value << (idx * 2));  in jz4730_config_pin_function()
3887 	regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);  in ingenic_get_pin_config()
3895 	struct ingenic_pinctrl *jzpc = jzgc->jzpc;  in ingenic_gpio_get_direction()
3896 	unsigned int pin = gc->base + offset;  in ingenic_gpio_get_direction()
3951 	seq_puts(p, gpio_chip->label);  in ingenic_gpio_irq_print_chip()
3974 	dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",  in ingenic_pinmux_set_pin_fn()
4012 		return -EINVAL;  in ingenic_pinmux_set_mux()
4016 		return -EINVAL;  in ingenic_pinmux_set_mux()
4018 	dev_dbg(pctldev->dev, "enable function %s group %s\n",  in ingenic_pinmux_set_mux()
4019 		func->func.name, grp->grp.name);  in ingenic_pinmux_set_mux()
4021 	mode = (uintptr_t)grp->data;  in ingenic_pinmux_set_mux()
4023 		for (i = 0; i < grp->grp.npins; i++)  in ingenic_pinmux_set_mux()
4024 			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode);  in ingenic_pinmux_set_mux()
4026 		pin_modes = grp->data;  in ingenic_pinmux_set_mux()
4028 		for (i = 0; i < grp->grp.npins; i++)  in ingenic_pinmux_set_mux()
4029 			ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]);  in ingenic_pinmux_set_mux()
4043 	dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",  in ingenic_pinmux_gpio_set_direction()
4090 				(jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
4093 				(jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
4096 		unsigned int half = PINS_PER_GPIO_CHIP / 2;  in ingenic_pinconf_get()
4097 		unsigned int idxh = (pin % half) * 2;  in ingenic_pinconf_get()
4100 			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_pinconf_get()
4103 			regmap_read(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_pinconf_get()
4108 		pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
4109 		pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
4121 		pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));  in ingenic_pinconf_get()
4122 		pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));  in ingenic_pinconf_get()
4128 			return -EINVAL;  in ingenic_pinconf_get()
4134 			return -EINVAL;  in ingenic_pinconf_get()
4140 			return -EINVAL;  in ingenic_pinconf_get()
4150 			return -EINVAL;  in ingenic_pinconf_get()
4161 			return -EINVAL;  in ingenic_pinconf_get()
4167 		return -ENOTSUPP;  in ingenic_pinconf_get()
4197 		unsigned int half = PINS_PER_GPIO_CHIP / 2;  in ingenic_set_bias()
4198 		unsigned int idxh = (pin % half) * 2;  in ingenic_set_bias()
4202 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
4204 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
4207 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
4209 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
4259 	unsigned int cfg, arg;  in ingenic_pinconf_set()  local
4262 	for (cfg = 0; cfg < num_configs; cfg++) {  in ingenic_pinconf_set()
4263 		switch (pinconf_to_config_param(configs[cfg])) {  in ingenic_pinconf_set()
4272 			return -ENOTSUPP;  in ingenic_pinconf_set()
4276 	for (cfg = 0; cfg < num_configs; cfg++) {  in ingenic_pinconf_set()
4277 		arg = pinconf_to_config_argument(configs[cfg]);  in ingenic_pinconf_set()
4279 		switch (pinconf_to_config_param(configs[cfg])) {  in ingenic_pinconf_set()
4281 			dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",  in ingenic_pinconf_set()
4287 			if (!(jzpc->info->pull_ups[offt] & BIT(idx)))  in ingenic_pinconf_set()
4288 				return -EINVAL;  in ingenic_pinconf_set()
4289 			dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",  in ingenic_pinconf_set()
4295 			if (!(jzpc->info->pull_downs[offt] & BIT(idx)))  in ingenic_pinconf_set()
4296 				return -EINVAL;  in ingenic_pinconf_set()
4297 			dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",  in ingenic_pinconf_set()
4304 				return -EINVAL;  in ingenic_pinconf_set()
4310 			ret = pinctrl_gpio_direction_output(jzpc->gc,  in ingenic_pinconf_set()
4311 							pin - jzpc->gc->base);  in ingenic_pinconf_set()
4320 				return -EINVAL;  in ingenic_pinconf_set()
4347 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
4351 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
4396 	{ .compatible = "ingenic,jz4730-gpio" },
4397 	{ .compatible = "ingenic,jz4740-gpio" },
4398 	{ .compatible = "ingenic,jz4725b-gpio" },
4399 	{ .compatible = "ingenic,jz4750-gpio" },
4400 	{ .compatible = "ingenic,jz4755-gpio" },
4401 	{ .compatible = "ingenic,jz4760-gpio" },
4402 	{ .compatible = "ingenic,jz4770-gpio" },
4403 	{ .compatible = "ingenic,jz4775-gpio" },
4404 	{ .compatible = "ingenic,jz4780-gpio" },
4405 	{ .compatible = "ingenic,x1000-gpio" },
4406 	{ .compatible = "ingenic,x1600-gpio" },
4407 	{ .compatible = "ingenic,x1830-gpio" },
4408 	{ .compatible = "ingenic,x2000-gpio" },
4409 	{ .compatible = "ingenic,x2100-gpio" },
4417 	struct device *dev = jzpc->dev;  in ingenic_gpio_probe()
4430 		return -ENOMEM;  in ingenic_gpio_probe()
4432 	jzpc->gc = &jzgc->gc;  in ingenic_gpio_probe()
4434 	jzgc->jzpc = jzpc;  in ingenic_gpio_probe()
4435 	jzgc->reg_base = bank * jzpc->info->reg_offset;  in ingenic_gpio_probe()
4437 	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);  in ingenic_gpio_probe()
4438 	if (!jzgc->gc.label)  in ingenic_gpio_probe()
4439 		return -ENOMEM;  in ingenic_gpio_probe()
4445 	jzgc->gc.base = bank * 32;  in ingenic_gpio_probe()
4447 	jzgc->gc.ngpio = 32;  in ingenic_gpio_probe()
4448 	jzgc->gc.parent = dev;  in ingenic_gpio_probe()
4449 	jzgc->gc.fwnode = fwnode;  in ingenic_gpio_probe()
4450 	jzgc->gc.owner = THIS_MODULE;  in ingenic_gpio_probe()
4452 	jzgc->gc.set = ingenic_gpio_set;  in ingenic_gpio_probe()
4453 	jzgc->gc.get = ingenic_gpio_get;  in ingenic_gpio_probe()
4454 	jzgc->gc.direction_input = pinctrl_gpio_direction_input;  in ingenic_gpio_probe()
4455 	jzgc->gc.direction_output = ingenic_gpio_direction_output;  in ingenic_gpio_probe()
4456 	jzgc->gc.get_direction = ingenic_gpio_get_direction;  in ingenic_gpio_probe()
4457 	jzgc->gc.request = gpiochip_generic_request;  in ingenic_gpio_probe()
4458 	jzgc->gc.free = gpiochip_generic_free;  in ingenic_gpio_probe()
4464 		return -EINVAL;  in ingenic_gpio_probe()
4465 	jzgc->irq = err;  in ingenic_gpio_probe()
4467 	girq = &jzgc->gc.irq;  in ingenic_gpio_probe()
4469 	girq->parent_handler = ingenic_gpio_irq_handler;  in ingenic_gpio_probe()
4470 	girq->num_parents = 1;  in ingenic_gpio_probe()
4471 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in ingenic_gpio_probe()
4473 	if (!girq->parents)  in ingenic_gpio_probe()
4474 		return -ENOMEM;  in ingenic_gpio_probe()
4476 	girq->parents[0] = jzgc->irq;  in ingenic_gpio_probe()
4477 	girq->default_type = IRQ_TYPE_NONE;  in ingenic_gpio_probe()
4478 	girq->handler = handle_level_irq;  in ingenic_gpio_probe()
4480 	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);  in ingenic_gpio_probe()
4489 	struct device *dev = &pdev->dev;  in ingenic_pinctrl_probe()
4502 		return -EINVAL;  in ingenic_pinctrl_probe()
4507 		return -ENOMEM;  in ingenic_pinctrl_probe()
4514 	if (chip_info->access_table) {  in ingenic_pinctrl_probe()
4515 		regmap_config.rd_table = chip_info->access_table;  in ingenic_pinctrl_probe()
4516 		regmap_config.wr_table = chip_info->access_table;  in ingenic_pinctrl_probe()
4518 		regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;  in ingenic_pinctrl_probe()
4521 	jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);  in ingenic_pinctrl_probe()
4522 	if (IS_ERR(jzpc->map)) {  in ingenic_pinctrl_probe()
4524 		return PTR_ERR(jzpc->map);  in ingenic_pinctrl_probe()
4527 	jzpc->dev = dev;  in ingenic_pinctrl_probe()
4528 	jzpc->info = chip_info;  in ingenic_pinctrl_probe()
4530 	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);  in ingenic_pinctrl_probe()
4532 		return -ENOMEM;  in ingenic_pinctrl_probe()
4535 	pctl_desc->name = dev_name(dev);  in ingenic_pinctrl_probe()
4536 	pctl_desc->owner = THIS_MODULE;  in ingenic_pinctrl_probe()
4537 	pctl_desc->pctlops = &ingenic_pctlops;  in ingenic_pinctrl_probe()
4538 	pctl_desc->pmxops = &ingenic_pmxops;  in ingenic_pinctrl_probe()
4539 	pctl_desc->confops = &ingenic_confops;  in ingenic_pinctrl_probe()
4540 	pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;  in ingenic_pinctrl_probe()
4541 	pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,  in ingenic_pinctrl_probe()
4542 			pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);  in ingenic_pinctrl_probe()
4543 	if (!jzpc->pdesc)  in ingenic_pinctrl_probe()
4544 		return -ENOMEM;  in ingenic_pinctrl_probe()
4546 	for (i = 0; i < pctl_desc->npins; i++) {  in ingenic_pinctrl_probe()
4547 		jzpc->pdesc[i].number = i;  in ingenic_pinctrl_probe()
4548 		jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",  in ingenic_pinctrl_probe()
4553 	jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);  in ingenic_pinctrl_probe()
4554 	if (IS_ERR(jzpc->pctl)) {  in ingenic_pinctrl_probe()
4556 		return PTR_ERR(jzpc->pctl);  in ingenic_pinctrl_probe()
4559 	for (i = 0; i < chip_info->num_groups; i++) {  in ingenic_pinctrl_probe()
4560 		const struct group_desc *group = &chip_info->groups[i];  in ingenic_pinctrl_probe()
4561 		const struct pingroup *grp = &group->grp;  in ingenic_pinctrl_probe()
4563 		err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins,  in ingenic_pinctrl_probe()
4564 						group->data);  in ingenic_pinctrl_probe()
4566 			dev_err(dev, "Failed to register group %s\n", grp->name);  in ingenic_pinctrl_probe()
4571 	for (i = 0; i < chip_info->num_functions; i++) {  in ingenic_pinctrl_probe()
4572 		const struct function_desc *function = &chip_info->functions[i];  in ingenic_pinctrl_probe()
4573 		const struct pinfunction *func = &function->func;  in ingenic_pinctrl_probe()
4575 		err = pinmux_generic_add_function(jzpc->pctl, func->name,  in ingenic_pinctrl_probe()
4576 						  func->groups, func->ngroups,  in ingenic_pinctrl_probe()
4577 						  function->data);  in ingenic_pinctrl_probe()
4579 			dev_err(dev, "Failed to register function %s\n", func->name);  in ingenic_pinctrl_probe()
4584 	dev_set_drvdata(dev, jzpc->map);  in ingenic_pinctrl_probe()
4599 #define IF_ENABLED(cfg, ptr)	PTR_IF(IS_ENABLED(cfg), (ptr))  argument
4603 		.compatible = "ingenic,jz4730-pinctrl",
4607 		.compatible = "ingenic,jz4740-pinctrl",
4611 		.compatible = "ingenic,jz4725b-pinctrl",
4615 		.compatible = "ingenic,jz4750-pinctrl",
4619 		.compatible = "ingenic,jz4755-pinctrl",
4623 		.compatible = "ingenic,jz4760-pinctrl",
4627 		.compatible = "ingenic,jz4760b-pinctrl",
4631 		.compatible = "ingenic,jz4770-pinctrl",
4635 		.compatible = "ingenic,jz4775-pinctrl",
4639 		.compatible = "ingenic,jz4780-pinctrl",
4643 		.compatible = "ingenic,x1000-pinctrl",
4647 		.compatible = "ingenic,x1000e-pinctrl",
4651 		.compatible = "ingenic,x1500-pinctrl",
4655 		.compatible = "ingenic,x1600-pinctrl",
4659 		.compatible = "ingenic,x1830-pinctrl",
4663 		.compatible = "ingenic,x2000-pinctrl",
4667 		.compatible = "ingenic,x2000e-pinctrl",
4671 		.compatible = "ingenic,x2100-pinctrl",
4679 		.name = "pinctrl-ingenic",