Lines Matching +full:pin +full:- +full:ctrl +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
133 struct ma35_pin_ctrl *ctrl; member
149 return npctl->ngroups; in ma35_get_groups_count()
156 return npctl->groups[selector].grp.name; in ma35_get_group_name()
164 if (selector >= npctl->ngroups) in ma35_get_group_pins()
165 return -EINVAL; in ma35_get_group_pins()
167 *pins = npctl->groups[selector].grp.pins; in ma35_get_group_pins()
168 *npins = npctl->groups[selector].grp.npins; in ma35_get_group_pins()
178 for (i = 0; i < npctl->ngroups; i++) { in ma35_pinctrl_find_group_by_name()
179 if (!strcmp(npctl->groups[i].grp.name, name)) in ma35_pinctrl_find_group_by_name()
180 return &npctl->groups[i]; in ma35_pinctrl_find_group_by_name()
202 grp = ma35_pinctrl_find_group_by_name(npctl, np->name); in ma35_pinctrl_dt_node_to_map_func()
204 dev_err(npctl->dev, "unable to find group for node %s\n", np->name); in ma35_pinctrl_dt_node_to_map_func()
205 return -EINVAL; in ma35_pinctrl_dt_node_to_map_func()
208 map_num += grp->grp.npins; in ma35_pinctrl_dt_node_to_map_func()
211 return -ENOMEM; in ma35_pinctrl_dt_node_to_map_func()
218 return -EINVAL; in ma35_pinctrl_dt_node_to_map_func()
220 setting = grp->data; in ma35_pinctrl_dt_node_to_map_func()
223 new_map[0].data.mux.function = parent->name; in ma35_pinctrl_dt_node_to_map_func()
224 new_map[0].data.mux.group = np->name; in ma35_pinctrl_dt_node_to_map_func()
228 for (i = 0; i < grp->grp.npins; i++) { in ma35_pinctrl_dt_node_to_map_func()
230 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->grp.pins[i]); in ma35_pinctrl_dt_node_to_map_func()
234 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in ma35_pinctrl_dt_node_to_map_func()
235 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in ma35_pinctrl_dt_node_to_map_func()
252 return npctl->nfunctions; in ma35_pinmux_get_func_count()
260 return npctl->functions[selector].name; in ma35_pinmux_get_func_name()
270 *groups = npctl->functions[function].groups; in ma35_pinmux_get_func_groups()
271 *num_groups = npctl->functions[function].ngroups; in ma35_pinmux_get_func_groups()
280 struct group_desc *grp = &npctl->groups[group]; in ma35_pinmux_set_mux()
281 struct ma35_pin_setting *setting = grp->data; in ma35_pinmux_set_mux()
284 dev_dbg(npctl->dev, "enable function %s group %s\n", in ma35_pinmux_set_mux()
285 npctl->functions[selector].name, grp->grp.name); in ma35_pinmux_set_mux()
287 for (i = 0; i < grp->grp.npins; i++) { in ma35_pinmux_set_mux()
288 regmap_read(npctl->regmap, setting->offset, ®val); in ma35_pinmux_set_mux()
289 regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1, in ma35_pinmux_set_mux()
290 setting->shift); in ma35_pinmux_set_mux()
291 regval |= setting->muxval << setting->shift; in ma35_pinmux_set_mux()
292 regmap_write(npctl->regmap, setting->offset, regval); in ma35_pinmux_set_mux()
326 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_in()
338 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_direction_out()
339 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_out()
359 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN; in ma35_gpio_core_get()
367 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_set()
385 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK; in ma35_gpio_core_to_request()
389 reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4; in ma35_gpio_core_to_request()
390 bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT; in ma35_gpio_core_to_request()
393 regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val); in ma35_gpio_core_to_request()
394 regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs); in ma35_gpio_core_to_request()
395 regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval); in ma35_gpio_core_to_request()
403 void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC; in ma35_irq_gpio_ack()
412 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN; in ma35_irq_gpio_mask()
426 void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE; in ma35_irq_gpio_unmask()
427 void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN; in ma35_irq_gpio_unmask()
431 bval = bank->irqtype & BIT(hwirq); in ma35_irq_gpio_unmask()
436 bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq); in ma35_irq_gpio_unmask()
450 bank->irqtype &= ~BIT(hwirq); in ma35_irq_irqtype()
451 bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq); in ma35_irq_irqtype()
456 bank->irqtype &= ~BIT(hwirq); in ma35_irq_irqtype()
457 bank->irqinten |= MA35_GP_INTEN_H(hwirq); in ma35_irq_irqtype()
458 bank->irqinten &= ~MA35_GP_INTEN_L(hwirq); in ma35_irq_irqtype()
463 bank->irqtype &= ~BIT(hwirq); in ma35_irq_irqtype()
464 bank->irqinten |= MA35_GP_INTEN_L(hwirq); in ma35_irq_irqtype()
465 bank->irqinten &= ~MA35_GP_INTEN_H(hwirq); in ma35_irq_irqtype()
468 return -EINVAL; in ma35_irq_irqtype()
471 writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE); in ma35_irq_irqtype()
472 writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN); in ma35_irq_irqtype()
478 .name = "MA35-GPIO-IRQ",
492 struct irq_domain *irqdomain = bank->chip.irq.domain; in ma35_irq_demux_intgroup()
499 isr = readl(bank->reg_base + MA35_GP_REG_INTSRC); in ma35_irq_demux_intgroup()
501 for_each_set_bit(offset, &isr, bank->nr_pins) in ma35_irq_demux_intgroup()
509 struct ma35_pin_ctrl *ctrl = npctl->ctrl; in ma35_gpiolib_register() local
510 struct ma35_pin_bank *bank = ctrl->pin_banks; in ma35_gpiolib_register()
514 for (i = 0; i < ctrl->nr_banks; i++, bank++) { in ma35_gpiolib_register()
515 if (!bank->valid) { in ma35_gpiolib_register()
516 dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode); in ma35_gpiolib_register()
519 bank->irqtype = 0; in ma35_gpiolib_register()
520 bank->irqinten = 0; in ma35_gpiolib_register()
521 bank->chip.label = bank->name; in ma35_gpiolib_register()
522 bank->chip.parent = &pdev->dev; in ma35_gpiolib_register()
523 bank->chip.request = ma35_gpio_core_to_request; in ma35_gpiolib_register()
524 bank->chip.direction_input = ma35_gpio_core_direction_in; in ma35_gpiolib_register()
525 bank->chip.direction_output = ma35_gpio_core_direction_out; in ma35_gpiolib_register()
526 bank->chip.get = ma35_gpio_core_get; in ma35_gpiolib_register()
527 bank->chip.set = ma35_gpio_core_set; in ma35_gpiolib_register()
528 bank->chip.base = -1; in ma35_gpiolib_register()
529 bank->chip.ngpio = bank->nr_pins; in ma35_gpiolib_register()
530 bank->chip.can_sleep = false; in ma35_gpiolib_register()
532 if (bank->irq > 0) { in ma35_gpiolib_register()
535 girq = &bank->chip.irq; in ma35_gpiolib_register()
537 girq->parent_handler = ma35_irq_demux_intgroup; in ma35_gpiolib_register()
538 girq->num_parents = 1; in ma35_gpiolib_register()
540 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, in ma35_gpiolib_register()
541 sizeof(*girq->parents), GFP_KERNEL); in ma35_gpiolib_register()
542 if (!girq->parents) in ma35_gpiolib_register()
543 return -ENOMEM; in ma35_gpiolib_register()
545 girq->parents[0] = bank->irq; in ma35_gpiolib_register()
546 girq->default_type = IRQ_TYPE_NONE; in ma35_gpiolib_register()
547 girq->handler = handle_bad_irq; in ma35_gpiolib_register()
550 ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); in ma35_gpiolib_register()
552 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", in ma35_gpiolib_register()
553 bank->chip.label, ret); in ma35_gpiolib_register()
562 bank->reg_base = fwnode_iomap(bank->fwnode, 0); in ma35_get_bank_data()
563 if (!bank->reg_base) in ma35_get_bank_data()
564 return -ENOMEM; in ma35_get_bank_data()
566 bank->irq = fwnode_irq_get(bank->fwnode, 0); in ma35_get_bank_data()
568 bank->nr_pins = MA35_GPIO_PORT_MAX; in ma35_get_bank_data()
570 bank->clk = of_clk_get(to_of_node(bank->fwnode), 0); in ma35_get_bank_data()
571 if (IS_ERR(bank->clk)) in ma35_get_bank_data()
572 return PTR_ERR(bank->clk); in ma35_get_bank_data()
574 return clk_prepare_enable(bank->clk); in ma35_get_bank_data()
580 struct ma35_pin_ctrl *ctrl; in ma35_pinctrl_get_soc_data() local
584 ctrl = pctl->ctrl; in ma35_pinctrl_get_soc_data()
585 ctrl->nr_banks = MA35_GPIO_BANK_MAX; in ma35_pinctrl_get_soc_data()
587 ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks, in ma35_pinctrl_get_soc_data()
588 sizeof(*ctrl->pin_banks), GFP_KERNEL); in ma35_pinctrl_get_soc_data()
589 if (!ctrl->pin_banks) in ma35_pinctrl_get_soc_data()
590 return -ENOMEM; in ma35_pinctrl_get_soc_data()
592 for (i = 0; i < ctrl->nr_banks; i++) { in ma35_pinctrl_get_soc_data()
593 ctrl->pin_banks[i].bank_num = i; in ma35_pinctrl_get_soc_data()
594 ctrl->pin_banks[i].name = gpio_group_name[i]; in ma35_pinctrl_get_soc_data()
597 for_each_gpiochip_node(&pdev->dev, child) { in ma35_pinctrl_get_soc_data()
598 bank = &ctrl->pin_banks[id]; in ma35_pinctrl_get_soc_data()
599 bank->fwnode = child; in ma35_pinctrl_get_soc_data()
600 bank->regmap = pctl->regmap; in ma35_pinctrl_get_soc_data()
601 bank->dev = &pdev->dev; in ma35_pinctrl_get_soc_data()
603 bank->valid = true; in ma35_pinctrl_get_soc_data()
616 static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin, in ma35_pinconf_set_pull() argument
623 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_pull()
624 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_pull()
649 static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin) in ma35_pinconf_get_output() argument
655 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_output()
656 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_output()
665 static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin) in ma35_pinconf_get_pull() argument
671 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_pull()
672 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_pull()
692 static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out) in ma35_pinconf_set_output() argument
697 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_output()
698 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_output()
705 static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin) in ma35_pinconf_get_power_source() argument
711 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_power_source()
712 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_power_source()
723 unsigned int pin, int arg) in ma35_pinconf_set_power_source() argument
730 return -EINVAL; in ma35_pinconf_set_power_source()
732 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_power_source()
733 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_power_source()
747 static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, in ma35_pinconf_get_drive_strength() argument
754 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_drive_strength()
755 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_drive_strength()
760 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) in ma35_pinconf_get_drive_strength()
768 static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin, in ma35_pinconf_set_drive_strength() argument
773 int i, ds_val = -1; in ma35_pinconf_set_drive_strength()
776 if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) { in ma35_pinconf_set_drive_strength()
791 if (ds_val == -1) in ma35_pinconf_set_drive_strength()
792 return -EINVAL; in ma35_pinconf_set_drive_strength()
794 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_drive_strength()
795 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_drive_strength()
806 static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin) in ma35_pinconf_get_schmitt_enable() argument
812 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_schmitt_enable()
813 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_schmitt_enable()
820 static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable) in ma35_pinconf_set_schmitt() argument
826 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_schmitt()
827 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_schmitt()
831 if (enable) in ma35_pinconf_set_schmitt()
841 static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin) in ma35_pinconf_get_slew_rate() argument
847 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_get_slew_rate()
848 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_get_slew_rate()
855 static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate) in ma35_pinconf_set_slew_rate() argument
861 ma35_gpio_cla_port(pin, &group_num, &port); in ma35_pinconf_set_slew_rate()
862 base = npctl->ctrl->pin_banks[group_num].reg_base; in ma35_pinconf_set_slew_rate()
873 static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) in ma35_pinconf_get() argument
884 if (ma35_pinconf_get_pull(npctl, pin) != param) in ma35_pinconf_get()
885 return -EINVAL; in ma35_pinconf_get()
890 ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg); in ma35_pinconf_get()
896 arg = ma35_pinconf_get_schmitt_enable(npctl, pin); in ma35_pinconf_get()
900 arg = ma35_pinconf_get_slew_rate(npctl, pin); in ma35_pinconf_get()
904 arg = ma35_pinconf_get_output(npctl, pin); in ma35_pinconf_get()
908 arg = ma35_pinconf_get_power_source(npctl, pin); in ma35_pinconf_get()
912 return -EINVAL; in ma35_pinconf_get()
919 static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, in ma35_pinconf_set() argument
935 ret = ma35_pinconf_set_pull(npctl, pin, param); in ma35_pinconf_set()
939 ret = ma35_pinconf_set_drive_strength(npctl, pin, arg); in ma35_pinconf_set()
943 ret = ma35_pinconf_set_schmitt(npctl, pin, 1); in ma35_pinconf_set()
947 ret = ma35_pinconf_set_schmitt(npctl, pin, arg); in ma35_pinconf_set()
951 ret = ma35_pinconf_set_slew_rate(npctl, pin, arg); in ma35_pinconf_set()
955 ret = ma35_pinconf_set_output(npctl, pin, arg); in ma35_pinconf_set()
959 ret = ma35_pinconf_set_power_source(npctl, pin, arg); in ma35_pinconf_set()
963 return -EINVAL; in ma35_pinconf_set()
982 struct ma35_pin_setting *pin; in ma35_pinctrl_parse_groups() local
995 return -EINVAL; in ma35_pinctrl_parse_groups()
997 elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL); in ma35_pinctrl_parse_groups()
999 return -ENOMEM; in ma35_pinctrl_parse_groups()
1001 grp->grp.name = np->name; in ma35_pinctrl_parse_groups()
1005 return -EINVAL; in ma35_pinctrl_parse_groups()
1006 grp->grp.npins = count / 3; in ma35_pinctrl_parse_groups()
1008 pins = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL); in ma35_pinctrl_parse_groups()
1010 return -ENOMEM; in ma35_pinctrl_parse_groups()
1011 grp->grp.pins = pins; in ma35_pinctrl_parse_groups()
1013 pin = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL); in ma35_pinctrl_parse_groups()
1014 if (!pin) in ma35_pinctrl_parse_groups()
1015 return -ENOMEM; in ma35_pinctrl_parse_groups()
1016 grp->data = pin; in ma35_pinctrl_parse_groups()
1019 pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE; in ma35_pinctrl_parse_groups()
1020 pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32; in ma35_pinctrl_parse_groups()
1021 pin->muxval = elems[i + 2]; in ma35_pinctrl_parse_groups()
1022 pin->configs = configs; in ma35_pinctrl_parse_groups()
1023 pin->nconfigs = nconfigs; in ma35_pinctrl_parse_groups()
1024 pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift); in ma35_pinctrl_parse_groups()
1025 pin++; in ma35_pinctrl_parse_groups()
1041 dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name); in ma35_pinctrl_parse_functions()
1043 func = &npctl->functions[index]; in ma35_pinctrl_parse_functions()
1044 func->name = np->name; in ma35_pinctrl_parse_functions()
1045 func->ngroups = of_get_child_count(np); in ma35_pinctrl_parse_functions()
1047 if (func->ngroups <= 0) in ma35_pinctrl_parse_functions()
1050 groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(*groups), GFP_KERNEL); in ma35_pinctrl_parse_functions()
1052 return -ENOMEM; in ma35_pinctrl_parse_functions()
1057 groups[i] = node->name; in ma35_pinctrl_parse_functions()
1058 grp = &npctl->groups[grp_index++]; in ma35_pinctrl_parse_functions()
1066 func->groups = groups; in ma35_pinctrl_parse_functions()
1072 struct device *dev = &pdev->dev; in ma35_pinctrl_probe_dt()
1078 npctl->nfunctions++; in ma35_pinctrl_probe_dt()
1079 npctl->ngroups += of_get_child_count(to_of_node(child)); in ma35_pinctrl_probe_dt()
1082 if (!npctl->nfunctions) in ma35_pinctrl_probe_dt()
1083 return -EINVAL; in ma35_pinctrl_probe_dt()
1085 npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions, in ma35_pinctrl_probe_dt()
1086 sizeof(*npctl->functions), GFP_KERNEL); in ma35_pinctrl_probe_dt()
1087 if (!npctl->functions) in ma35_pinctrl_probe_dt()
1088 return -ENOMEM; in ma35_pinctrl_probe_dt()
1090 npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups, in ma35_pinctrl_probe_dt()
1091 sizeof(*npctl->groups), GFP_KERNEL); in ma35_pinctrl_probe_dt()
1092 if (!npctl->groups) in ma35_pinctrl_probe_dt()
1093 return -ENOMEM; in ma35_pinctrl_probe_dt()
1099 dev_err(&pdev->dev, "failed to parse function\n"); in ma35_pinctrl_probe_dt()
1109 struct device *dev = &pdev->dev; in ma35_pinctrl_probe()
1113 if (!info || !info->pins || !info->npins) { in ma35_pinctrl_probe()
1114 dev_err(&pdev->dev, "wrong pinctrl info\n"); in ma35_pinctrl_probe()
1115 return -EINVAL; in ma35_pinctrl_probe()
1118 npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL); in ma35_pinctrl_probe()
1120 return -ENOMEM; in ma35_pinctrl_probe()
1122 ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL); in ma35_pinctrl_probe()
1124 return -ENOMEM; in ma35_pinctrl_probe()
1126 npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL); in ma35_pinctrl_probe()
1127 if (!npctl->ctrl) in ma35_pinctrl_probe()
1128 return -ENOMEM; in ma35_pinctrl_probe()
1130 ma35_pinctrl_desc->name = dev_name(&pdev->dev); in ma35_pinctrl_probe()
1131 ma35_pinctrl_desc->pins = info->pins; in ma35_pinctrl_probe()
1132 ma35_pinctrl_desc->npins = info->npins; in ma35_pinctrl_probe()
1133 ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops; in ma35_pinctrl_probe()
1134 ma35_pinctrl_desc->pmxops = &ma35_pmx_ops; in ma35_pinctrl_probe()
1135 ma35_pinctrl_desc->confops = &ma35_pinconf_ops; in ma35_pinctrl_probe()
1136 ma35_pinctrl_desc->owner = THIS_MODULE; in ma35_pinctrl_probe()
1138 npctl->info = info; in ma35_pinctrl_probe()
1139 npctl->dev = &pdev->dev; in ma35_pinctrl_probe()
1141 npctl->regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys"); in ma35_pinctrl_probe()
1142 if (IS_ERR(npctl->regmap)) in ma35_pinctrl_probe()
1143 return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap), in ma35_pinctrl_probe()
1148 return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n"); in ma35_pinctrl_probe()
1154 return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n"); in ma35_pinctrl_probe()
1156 ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl); in ma35_pinctrl_probe()
1158 return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n"); in ma35_pinctrl_probe()
1160 ret = pinctrl_enable(npctl->pctl); in ma35_pinctrl_probe()
1162 return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n"); in ma35_pinctrl_probe()
1171 return pinctrl_force_sleep(npctl->pctl); in ma35_pinctrl_suspend()
1178 return pinctrl_force_default(npctl->pctl); in ma35_pinctrl_resume()