1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK		0x3f
24 #define HS_TERM_RANGE_ADJ_MASK		0xf
26 #define HS_SQUELCH_MASK			0x7
28 #define RPD_CTRL_SHIFT			0
29 #define RPD_CTRL_MASK			0x1f
32 #define XUSB_PADCTL_USB2_PAD_MUX	0x4
34 #define  USB2_PORT_MASK			0x3
37 #define  HSIC_PORT_MASK			0x1
38 #define   PORT_HSIC			0
40 #define XUSB_PADCTL_USB2_PORT_CAP	0x8
41 #define XUSB_PADCTL_SS_PORT_CAP		0xc
43 #define  PORT_CAP_MASK			0x3
44 #define   PORT_CAP_DISABLED		0x0
45 #define   PORT_CAP_HOST			0x1
46 #define   PORT_CAP_DEVICE		0x2
47 #define   PORT_CAP_OTG			0x3
49 #define XUSB_PADCTL_ELPG_PROGRAM		0x20
57 	(USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |	\
58 	USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) |		\
60 	USB2_HSIC_PORT_WAKEUP_EVENT(0))
62 #define XUSB_PADCTL_ELPG_PROGRAM_1		0x24
63 #define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG			0x2c
68 #define   PORTX_SPEED_SUPPORT_MASK		(0x3)
69 #define     PORT_SPEED_SUPPORT_GEN1		(0x0)
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
72 #define  HS_CURR_LEVEL(x)			((x) & 0x3f)
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x)	(0x8c + (x) * 0x40)
81 #define  TERM_RANGE_ADJ(x)			(((x) & 0xf) << 3)
82 #define  RPD_CTRL(x)				(((x) & 0x1f) << 26)
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284
86 #define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288
89 #define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
90 #define  USB2_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 19)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL2		0x28c
95 #define  USB2_TRK_HW_MODE			BIT(0)
98 #define XUSB_PADCTL_HSIC_PADX_CTL0(x)		(0x300 + (x) * 0x20)
110 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0		0x340
111 #define  HSIC_TRK_START_TIMER(x)		(((x) & 0x7f) << 5)
112 #define  HSIC_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 12)
115 #define USB2_VBUS_ID				0x360
117 #define  ID_OVERRIDE(x)				(((x) & 0xf) << 18)
119 #define  ID_OVERRIDE_GROUNDED			ID_OVERRIDE(0)
122 #define XUSB_AO_USB_DEBOUNCE_DEL		(0x4)
123 #define   UHSIC_LINE_DEB_CNT(x)			(((x) & 0xf) << 4)
124 #define   UTMIP_LINE_DEB_CNT(x)			((x) & 0xf)
126 #define XUSB_AO_UTMIP_TRIGGERS(x)		(0x40 + (x) * 4)
127 #define   CLR_WALK_PTR				BIT(0)
131 #define XUSB_AO_UHSIC_TRIGGERS(x)		(0x60 + (x) * 4)
132 #define   HSIC_CLR_WALK_PTR			BIT(0)
136 #define XUSB_AO_UTMIP_SAVED_STATE(x)		(0x70 + (x) * 4)
137 #define   SPEED(x)				((x) & 0x3)
138 #define     UTMI_HS				SPEED(0)
143 #define XUSB_AO_UHSIC_SAVED_STATE(x)		(0x90 + (x) * 4)
144 #define   MODE(x)				((x) & 0x1)
145 #define   MODE_HS				MODE(0)
148 #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x)	(0xa0 + (x) * 4)
150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x)		(0xd0 + (x) * 4)
151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x)		(0xf0 + (x) * 4)
152 #define   FAKE_USBOP_VAL			BIT(0)
156 #define   FAKE_STROBE_VAL			BIT(0)
163 #define   WAKE_VAL(x)				(((x) & 0xf) << 17)
170 #define XUSB_AO_UTMIP_SLEEPWALK(x)		(0x100 + (x) * 4)
172 #define   USBOP_RPD_A				BIT(0)
202 #define XUSB_AO_UHSIC_SLEEPWALK(x)		(0x120 + (x) * 4)
204 #define   RPD_STROBE_A				BIT(0)
224 #define XUSB_AO_UTMIP_PAD_CFG(x)		(0x130 + (x) * 4)
235 #define XUSB_AO_UHSIC_PAD_CFG(x)		(0x150 + (x) * 4)
236 #define   STROBE_VAL_PD				BIT(0)
282 	writel(value, priv->ao_regs + offset);  in ao_writel()
287 	return readl(priv->ao_regs + offset);  in ao_readl()
301 	struct tegra_xusb_usb2_lane *usb2;  in tegra186_usb2_lane_probe()  local
304 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);  in tegra186_usb2_lane_probe()
305 	if (!usb2)  in tegra186_usb2_lane_probe()
306 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_lane_probe()
308 	INIT_LIST_HEAD(&usb2->base.list);  in tegra186_usb2_lane_probe()
309 	usb2->base.soc = &pad->soc->lanes[index];  in tegra186_usb2_lane_probe()
310 	usb2->base.index = index;  in tegra186_usb2_lane_probe()
311 	usb2->base.pad = pad;  in tegra186_usb2_lane_probe()
312 	usb2->base.np = np;  in tegra186_usb2_lane_probe()
314 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);  in tegra186_usb2_lane_probe()
315 	if (err < 0) {  in tegra186_usb2_lane_probe()
316 		kfree(usb2);  in tegra186_usb2_lane_probe()
320 	return &usb2->base;  in tegra186_usb2_lane_probe()
325 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);  in tegra186_usb2_lane_remove()  local
327 	kfree(usb2);  in tegra186_usb2_lane_remove()
333 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_sleepwalk()
335 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_sleepwalk()
338 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
352 	value &= ~UTMIP_LINE_DEB_CNT(~0);  in tegra186_utmi_enable_phy_sleepwalk()
369 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_enable_phy_sleepwalk()
380 	value &= ~SPEED(~0);  in tegra186_utmi_enable_phy_sleepwalk()
409 	 * as well as capture the configuration of the USB2.0 pad  in tegra186_utmi_enable_phy_sleepwalk()
415 	/* setup the pull-ups and pull-downs of the signals during the four  in tegra186_utmi_enable_phy_sleepwalk()
426 		/* J state: D+/D- = high/low, K state: D+/D- = low/high */  in tegra186_utmi_enable_phy_sleepwalk()
430 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
435 		/* J state: D+/D- = low/high, K state: D+/D- = high/low */  in tegra186_utmi_enable_phy_sleepwalk()
439 		if (padctl->soc->supports_lp_cfg_en)  in tegra186_utmi_enable_phy_sleepwalk()
457 	/* switch the electric control of the USB2.0 pad to XUSB_AO */  in tegra186_utmi_enable_phy_sleepwalk()
465 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_enable_phy_sleepwalk()
474 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_sleepwalk()
476 	return 0;  in tegra186_utmi_enable_phy_sleepwalk()
481 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_sleepwalk()
483 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_sleepwalk()
486 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
493 	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */  in tegra186_utmi_disable_phy_sleepwalk()
501 	value &= ~WAKE_VAL(~0);  in tegra186_utmi_disable_phy_sleepwalk()
505 	if (padctl->soc->supports_lp_cfg_en) {  in tegra186_utmi_disable_phy_sleepwalk()
522 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_sleepwalk()
524 	return 0;  in tegra186_utmi_disable_phy_sleepwalk()
529 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_enable_phy_wake()
530 	unsigned int index = lane->index;  in tegra186_utmi_enable_phy_wake()
533 	mutex_lock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
547 	mutex_unlock(&padctl->lock);  in tegra186_utmi_enable_phy_wake()
549 	return 0;  in tegra186_utmi_enable_phy_wake()
554 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_disable_phy_wake()
555 	unsigned int index = lane->index;  in tegra186_utmi_disable_phy_wake()
558 	mutex_lock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
572 	mutex_unlock(&padctl->lock);  in tegra186_utmi_disable_phy_wake()
574 	return 0;  in tegra186_utmi_disable_phy_wake()
579 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_remote_wake_detected()
580 	unsigned int index = lane->index;  in tegra186_utmi_phy_remote_wake_detected()
604 	struct device *dev = padctl->dev;  in tegra186_utmi_bias_pad_power_on()
608 	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))  in tegra186_utmi_bias_pad_power_on()
611 	err = clk_prepare_enable(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
612 	if (err < 0)  in tegra186_utmi_bias_pad_power_on()
613 		dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);  in tegra186_utmi_bias_pad_power_on()
616 	value &= ~USB2_TRK_START_TIMER(~0);  in tegra186_utmi_bias_pad_power_on()
617 	value |= USB2_TRK_START_TIMER(0x1e);  in tegra186_utmi_bias_pad_power_on()
618 	value &= ~USB2_TRK_DONE_RESET_TIMER(~0);  in tegra186_utmi_bias_pad_power_on()
619 	value |= USB2_TRK_DONE_RESET_TIMER(0xa);  in tegra186_utmi_bias_pad_power_on()
624 	value &= ~HS_SQUELCH_LEVEL(~0);  in tegra186_utmi_bias_pad_power_on()
625 	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);  in tegra186_utmi_bias_pad_power_on()
634 	if (padctl->soc->poll_trk_completed) {  in tegra186_utmi_bias_pad_power_on()
641 			dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err);  in tegra186_utmi_bias_pad_power_on()
651 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_on()
657 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_on()
666 	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))  in tegra186_utmi_bias_pad_power_off()
673 	if (padctl->soc->trk_hw_mode) {  in tegra186_utmi_bias_pad_power_off()
677 		clk_disable_unprepare(priv->usb2_trk_clk);  in tegra186_utmi_bias_pad_power_off()
685 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_on()
688 	struct device *dev = padctl->dev;  in tegra186_utmi_pad_power_on()
689 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_on()
695 	mutex_lock(&padctl->lock);  in tegra186_utmi_pad_power_on()
696 	if (test_bit(index, priv->utmi_pad_enabled)) {  in tegra186_utmi_pad_power_on()
697 		mutex_unlock(&padctl->lock);  in tegra186_utmi_pad_power_on()
703 		dev_err(dev, "no port found for USB2 lane %u\n", index);  in tegra186_utmi_pad_power_on()
704 		mutex_unlock(&padctl->lock);  in tegra186_utmi_pad_power_on()
722 	set_bit(index, priv->utmi_pad_enabled);  in tegra186_utmi_pad_power_on()
723 	mutex_unlock(&padctl->lock);  in tegra186_utmi_pad_power_on()
729 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_pad_power_down()
731 	unsigned int index = lane->index;  in tegra186_utmi_pad_power_down()
737 	mutex_lock(&padctl->lock);  in tegra186_utmi_pad_power_down()
738 	if (!test_bit(index, priv->utmi_pad_enabled)) {  in tegra186_utmi_pad_power_down()
739 		mutex_unlock(&padctl->lock);  in tegra186_utmi_pad_power_down()
743 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);  in tegra186_utmi_pad_power_down()
755 	clear_bit(index, priv->utmi_pad_enabled);  in tegra186_utmi_pad_power_down()
759 	mutex_unlock(&padctl->lock);  in tegra186_utmi_pad_power_down()
767 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_vbus_override()
773 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_vbus_override()
781 	return 0;  in tegra186_xusb_padctl_vbus_override()
789 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");  in tegra186_xusb_padctl_id_override()
802 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_id_override()
805 		value &= ~ID_OVERRIDE(~0);  in tegra186_xusb_padctl_id_override()
811 	return 0;  in tegra186_xusb_padctl_id_override()
818 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_set_mode()
820 								lane->index);  in tegra186_utmi_phy_set_mode()
821 	int err = 0;  in tegra186_utmi_phy_set_mode()
823 	mutex_lock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
825 	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);  in tegra186_utmi_phy_set_mode()
831 			err = regulator_enable(port->supply);  in tegra186_utmi_phy_set_mode()
840 			if (regulator_is_enabled(port->supply))  in tegra186_utmi_phy_set_mode()
841 				regulator_disable(port->supply);  in tegra186_utmi_phy_set_mode()
848 	mutex_unlock(&padctl->lock);  in tegra186_utmi_phy_set_mode()
856 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);  in tegra186_utmi_phy_power_on()  local
857 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_power_on()
860 	unsigned int index = lane->index;  in tegra186_utmi_phy_power_on()
861 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_power_on()
866 		dev_err(dev, "no port found for USB2 lane %u\n", index);  in tegra186_utmi_phy_power_on()
867 		return -ENODEV;  in tegra186_utmi_phy_power_on()
878 	if (port->mode == USB_DR_MODE_UNKNOWN)  in tegra186_utmi_phy_power_on()
880 	else if (port->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_utmi_phy_power_on()
882 	else if (port->mode == USB_DR_MODE_HOST)  in tegra186_utmi_phy_power_on()
884 	else if (port->mode == USB_DR_MODE_OTG)  in tegra186_utmi_phy_power_on()
892 	value &= ~HS_CURR_LEVEL(~0);  in tegra186_utmi_phy_power_on()
894 	if (usb2->hs_curr_level_offset) {  in tegra186_utmi_phy_power_on()
897 		hs_current_level = (int)priv->calib.hs_curr_level[index] +  in tegra186_utmi_phy_power_on()
898 						usb2->hs_curr_level_offset;  in tegra186_utmi_phy_power_on()
900 		if (hs_current_level < 0)  in tegra186_utmi_phy_power_on()
901 			hs_current_level = 0;  in tegra186_utmi_phy_power_on()
902 		if (hs_current_level > 0x3f)  in tegra186_utmi_phy_power_on()
903 			hs_current_level = 0x3f;  in tegra186_utmi_phy_power_on()
907 		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);  in tegra186_utmi_phy_power_on()
913 	value &= ~TERM_RANGE_ADJ(~0);  in tegra186_utmi_phy_power_on()
914 	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);  in tegra186_utmi_phy_power_on()
915 	value &= ~RPD_CTRL(~0);  in tegra186_utmi_phy_power_on()
916 	value |= RPD_CTRL(priv->calib.rpd_ctrl);  in tegra186_utmi_phy_power_on()
921 	return 0;  in tegra186_utmi_phy_power_on()
928 	return 0;  in tegra186_utmi_phy_power_off()
934 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_init()
936 	unsigned int index = lane->index;  in tegra186_utmi_phy_init()
937 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_init()
943 		dev_err(dev, "no port found for USB2 lane %u\n", index);  in tegra186_utmi_phy_init()
944 		return -ENODEV;  in tegra186_utmi_phy_init()
947 	if (port->mode == USB_DR_MODE_OTG ||  in tegra186_utmi_phy_init()
948 	    port->mode == USB_DR_MODE_PERIPHERAL) {  in tegra186_utmi_phy_init()
952 		reg &= ~ID_OVERRIDE(~0);  in tegra186_utmi_phy_init()
957 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_init()
958 		err = regulator_enable(port->supply);  in tegra186_utmi_phy_init()
966 	return 0;  in tegra186_utmi_phy_init()
972 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_utmi_phy_exit()
974 	unsigned int index = lane->index;  in tegra186_utmi_phy_exit()
975 	struct device *dev = padctl->dev;  in tegra186_utmi_phy_exit()
980 		dev_err(dev, "no port found for USB2 lane %u\n", index);  in tegra186_utmi_phy_exit()
981 		return -ENODEV;  in tegra186_utmi_phy_exit()
984 	if (port->supply && port->mode == USB_DR_MODE_HOST) {  in tegra186_utmi_phy_exit()
985 		err = regulator_disable(port->supply);  in tegra186_utmi_phy_exit()
993 	return 0;  in tegra186_utmi_phy_exit()
1011 	struct tegra_xusb_usb2_pad *usb2;  in tegra186_usb2_pad_probe()  local
1015 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);  in tegra186_usb2_pad_probe()
1016 	if (!usb2)  in tegra186_usb2_pad_probe()
1017 		return ERR_PTR(-ENOMEM);  in tegra186_usb2_pad_probe()
1019 	pad = &usb2->base;  in tegra186_usb2_pad_probe()
1020 	pad->ops = &tegra186_usb2_lane_ops;  in tegra186_usb2_pad_probe()
1021 	pad->soc = soc;  in tegra186_usb2_pad_probe()
1024 	if (err < 0) {  in tegra186_usb2_pad_probe()
1025 		kfree(usb2);  in tegra186_usb2_pad_probe()
1029 	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");  in tegra186_usb2_pad_probe()
1030 	if (IS_ERR(priv->usb2_trk_clk)) {  in tegra186_usb2_pad_probe()
1031 		err = PTR_ERR(priv->usb2_trk_clk);  in tegra186_usb2_pad_probe()
1032 		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);  in tegra186_usb2_pad_probe()
1037 	if (err < 0)  in tegra186_usb2_pad_probe()
1040 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb2_pad_probe()
1045 	device_unregister(&pad->dev);  in tegra186_usb2_pad_probe()
1052 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);  in tegra186_usb2_pad_remove()  local
1054 	kfree(usb2);  in tegra186_usb2_pad_remove()
1068 	return 0;  in tegra186_usb2_port_enable()
1078 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);  in tegra186_usb2_port_map()
1099 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_lane_probe()
1101 	INIT_LIST_HEAD(&usb3->base.list);  in tegra186_usb3_lane_probe()
1102 	usb3->base.soc = &pad->soc->lanes[index];  in tegra186_usb3_lane_probe()
1103 	usb3->base.index = index;  in tegra186_usb3_lane_probe()
1104 	usb3->base.pad = pad;  in tegra186_usb3_lane_probe()
1105 	usb3->base.np = np;  in tegra186_usb3_lane_probe()
1107 	err = tegra_xusb_lane_parse_dt(&usb3->base, np);  in tegra186_usb3_lane_probe()
1108 	if (err < 0) {  in tegra186_usb3_lane_probe()
1113 	return &usb3->base;  in tegra186_usb3_lane_probe()
1126 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_sleepwalk()
1127 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_sleepwalk()
1130 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1144 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_sleepwalk()
1146 	return 0;  in tegra186_usb3_enable_phy_sleepwalk()
1151 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_sleepwalk()
1152 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_sleepwalk()
1155 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1167 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_sleepwalk()
1169 	return 0;  in tegra186_usb3_disable_phy_sleepwalk()
1174 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_enable_phy_wake()
1175 	unsigned int index = lane->index;  in tegra186_usb3_enable_phy_wake()
1178 	mutex_lock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1192 	mutex_unlock(&padctl->lock);  in tegra186_usb3_enable_phy_wake()
1194 	return 0;  in tegra186_usb3_enable_phy_wake()
1199 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_disable_phy_wake()
1200 	unsigned int index = lane->index;  in tegra186_usb3_disable_phy_wake()
1203 	mutex_lock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1217 	mutex_unlock(&padctl->lock);  in tegra186_usb3_disable_phy_wake()
1219 	return 0;  in tegra186_usb3_disable_phy_wake()
1224 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_remote_wake_detected()
1225 	unsigned int index = lane->index;  in tegra186_usb3_phy_remote_wake_detected()
1247 	return 0;  in tegra186_usb3_port_enable()
1257 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);  in tegra186_usb3_port_map()
1270 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_on()
1272 	struct tegra_xusb_usb2_port *usb2;  in tegra186_usb3_phy_power_on()  local
1273 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_on()
1274 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_on()
1280 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1283 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);  in tegra186_usb3_phy_power_on()
1284 	if (!usb2) {  in tegra186_usb3_phy_power_on()
1287 		return -ENODEV;  in tegra186_usb3_phy_power_on()
1290 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1295 	if (usb2->mode == USB_DR_MODE_UNKNOWN)  in tegra186_usb3_phy_power_on()
1297 	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)  in tegra186_usb3_phy_power_on()
1299 	else if (usb2->mode == USB_DR_MODE_HOST)  in tegra186_usb3_phy_power_on()
1301 	else if (usb2->mode == USB_DR_MODE_OTG)  in tegra186_usb3_phy_power_on()
1306 	if (padctl->soc->supports_gen2 && port->disable_gen2) {  in tegra186_usb3_phy_power_on()
1331 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_on()
1333 	return 0;  in tegra186_usb3_phy_power_on()
1339 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra186_usb3_phy_power_off()
1341 	unsigned int index = lane->index;  in tegra186_usb3_phy_power_off()
1342 	struct device *dev = padctl->dev;  in tegra186_usb3_phy_power_off()
1348 		return -ENODEV;  in tegra186_usb3_phy_power_off()
1351 	mutex_lock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1369 	mutex_unlock(&padctl->lock);  in tegra186_usb3_phy_power_off()
1371 	return 0;  in tegra186_usb3_phy_power_off()
1376 	return 0;  in tegra186_usb3_phy_init()
1381 	return 0;  in tegra186_usb3_phy_exit()
1403 		return ERR_PTR(-ENOMEM);  in tegra186_usb3_pad_probe()
1405 	pad = &usb3->base;  in tegra186_usb3_pad_probe()
1406 	pad->ops = &tegra186_usb3_lane_ops;  in tegra186_usb3_pad_probe()
1407 	pad->soc = soc;  in tegra186_usb3_pad_probe()
1410 	if (err < 0) {  in tegra186_usb3_pad_probe()
1416 	if (err < 0)  in tegra186_usb3_pad_probe()
1419 	dev_set_drvdata(&pad->dev, pad);  in tegra186_usb3_pad_probe()
1424 	device_unregister(&pad->dev);  in tegra186_usb3_pad_probe()
1431 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);  in tegra186_usb3_pad_remove()  local
1433 	kfree(usb2);  in tegra186_usb3_pad_remove()
1448 	struct device *dev = padctl->base.dev;  in tegra186_xusb_read_fuse_calibration()
1453 	count = padctl->base.soc->ports.usb2.count;  in tegra186_xusb_read_fuse_calibration()
1457 		return -ENOMEM;  in tegra186_xusb_read_fuse_calibration()
1466 	for (i = 0; i < count; i++)  in tegra186_xusb_read_fuse_calibration()
1470 	padctl->calib.hs_curr_level = level;  in tegra186_xusb_read_fuse_calibration()
1472 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1474 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &  in tegra186_xusb_read_fuse_calibration()
1485 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;  in tegra186_xusb_read_fuse_calibration()
1487 	return 0;  in tegra186_xusb_read_fuse_calibration()
1501 		return ERR_PTR(-ENOMEM);  in tegra186_xusb_padctl_probe()
1503 	priv->base.dev = dev;  in tegra186_xusb_padctl_probe()
1504 	priv->base.soc = soc;  in tegra186_xusb_padctl_probe()
1507 	priv->ao_regs = devm_ioremap_resource(dev, res);  in tegra186_xusb_padctl_probe()
1508 	if (IS_ERR(priv->ao_regs))  in tegra186_xusb_padctl_probe()
1509 		return ERR_CAST(priv->ao_regs);  in tegra186_xusb_padctl_probe()
1512 	if (err < 0)  in tegra186_xusb_padctl_probe()
1515 	return &priv->base;  in tegra186_xusb_padctl_probe()
1522 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);  in tegra186_xusb_padctl_save()
1523 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_save()
1524 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_save()
1525 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_save()
1532 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);  in tegra186_xusb_padctl_restore()
1533 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);  in tegra186_xusb_padctl_restore()
1534 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);  in tegra186_xusb_padctl_restore()
1535 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);  in tegra186_xusb_padctl_restore()
1542 	return 0;  in tegra186_xusb_padctl_suspend_noirq()
1549 	return 0;  in tegra186_xusb_padctl_resume_noirq()
1568 	"avdd-pll-erefeut",
1569 	"avdd-usb",
1570 	"vclamp-usb",
1571 	"vddio-hsic",
1575 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1576 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1577 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1581 	.name = "usb2",
1588 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1589 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1590 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1603 #if 0 /* TODO implement */
1612 		.usb2 = {
1616 #if 0 /* TODO implement */
1637 	"avdd-usb",
1638 	"vclamp-usb",
1642 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1643 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1644 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1645 	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1649 	.name = "usb2",
1656 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1657 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1658 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1659 	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1678 		.usb2 = {
1699 		.usb2 = {