Lines Matching +full:pre +full:- +full:emphasis
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
129 /* vo-grf */
179 bool hs; /* flag for high-speed */
206 /* voltage swing 0, pre-emphasis 0->3 */
214 /* voltage swing 1, pre-emphasis 0->2 */
221 /* voltage swing 2, pre-emphasis 0->1 */
227 /* voltage swing 3, pre-emphasis 0 */
234 /* voltage swing 0, pre-emphasis 0->3 */
242 /* voltage swing 1, pre-emphasis 0->2 */
249 /* voltage swing 2, pre-emphasis 0->1 */
255 /* voltage swing 3, pre-emphasis 0 */
262 /* voltage swing 0, pre-emphasis 0->3 */
270 /* voltage swing 1, pre-emphasis 0->2 */
277 /* voltage swing 2, pre-emphasis 0->1 */
283 /* voltage swing 3, pre-emphasis 0 */
290 /* voltage swing 0, pre-emphasis 0->3 */
298 /* voltage swing 1, pre-emphasis 0->2 */
305 /* voltage swing 2, pre-emphasis 0->1 */
311 /* voltage swing 3, pre-emphasis 0 */
422 return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); in rk_udphy_grfreg_write()
429 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); in rk_udphy_clk_init()
430 if (udphy->num_clks < 1) in rk_udphy_clk_init()
431 return -ENODEV; in rk_udphy_clk_init()
434 for (i = 0; i < udphy->num_clks; i++) { in rk_udphy_clk_init()
435 if (!strncmp(udphy->clks[i].id, "refclk", 6)) { in rk_udphy_clk_init()
436 udphy->refclk = udphy->clks[i].clk; in rk_udphy_clk_init()
441 if (!udphy->refclk) in rk_udphy_clk_init()
442 return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); in rk_udphy_clk_init()
449 return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); in rk_udphy_reset_assert_all()
454 return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); in rk_udphy_reset_deassert_all()
459 struct reset_control_bulk_data *list = udphy->rsts; in rk_udphy_reset_deassert()
462 for (idx = 0; idx < udphy->num_rsts; idx++) { in rk_udphy_reset_deassert()
467 return -EINVAL; in rk_udphy_reset_deassert()
472 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_reset_init()
475 udphy->num_rsts = cfg->num_rsts; in rk_udphy_reset_init()
476 udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, in rk_udphy_reset_init()
477 sizeof(*udphy->rsts), GFP_KERNEL); in rk_udphy_reset_init()
478 if (!udphy->rsts) in rk_udphy_reset_init()
479 return -ENOMEM; in rk_udphy_reset_init()
481 for (idx = 0; idx < cfg->num_rsts; idx++) in rk_udphy_reset_init()
482 udphy->rsts[idx].id = cfg->rst_list[idx]; in rk_udphy_reset_init()
484 return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, in rk_udphy_reset_init()
485 udphy->rsts); in rk_udphy_reset_init()
490 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_u3_port_disable()
493 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; in rk_udphy_u3_port_disable()
494 rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); in rk_udphy_u3_port_disable()
499 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_usb_bvalid_enable()
501 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); in rk_udphy_usb_bvalid_enable()
502 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); in rk_udphy_usb_bvalid_enable()
508 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
509 * ---------------------------------------------------------------------------
510 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
520 * ---------------------------------------------------------------------------
523 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
525 * ---------------------------------------------------------------------------
526 * B11-B10 A2-A3 A11-A10 B2-B3
527 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
530 * ---------------------------------------------------------------------------
531 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
533 * ---------------------------------------------------------------------------
534 * B11-B10 A2-A3 A11-A10 B2-B3
535 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
538 * ---------------------------------------------------------------------------
543 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_dplane_select()
546 switch (udphy->mode) { in rk_udphy_dplane_select()
548 value |= 2 << udphy->dp_lane_sel[2] * 2; in rk_udphy_dplane_select()
549 value |= 3 << udphy->dp_lane_sel[3] * 2; in rk_udphy_dplane_select()
553 value |= 0 << udphy->dp_lane_sel[0] * 2; in rk_udphy_dplane_select()
554 value |= 1 << udphy->dp_lane_sel[1] * 2; in rk_udphy_dplane_select()
564 regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, in rk_udphy_dplane_select()
566 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | in rk_udphy_dplane_select()
567 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); in rk_udphy_dplane_select()
574 switch (udphy->mode) { in rk_udphy_dplane_get()
598 val |= BIT(udphy->dp_lane_sel[i]); in rk_udphy_dplane_enable()
600 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, in rk_udphy_dplane_enable()
604 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk_udphy_dplane_enable()
610 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_dp_hpd_event_trigger()
612 udphy->dp_sink_hpd_sel = true; in rk_udphy_dp_hpd_event_trigger()
613 udphy->dp_sink_hpd_cfg = hpd; in rk_udphy_dp_hpd_event_trigger()
615 if (!udphy->dp_in_use) in rk_udphy_dp_hpd_event_trigger()
618 rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); in rk_udphy_dp_hpd_event_trigger()
623 if (udphy->flip) { in rk_udphy_set_typec_default_mapping()
624 udphy->dp_lane_sel[0] = 0; in rk_udphy_set_typec_default_mapping()
625 udphy->dp_lane_sel[1] = 1; in rk_udphy_set_typec_default_mapping()
626 udphy->dp_lane_sel[2] = 3; in rk_udphy_set_typec_default_mapping()
627 udphy->dp_lane_sel[3] = 2; in rk_udphy_set_typec_default_mapping()
628 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_set_typec_default_mapping()
629 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; in rk_udphy_set_typec_default_mapping()
630 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; in rk_udphy_set_typec_default_mapping()
631 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; in rk_udphy_set_typec_default_mapping()
632 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; in rk_udphy_set_typec_default_mapping()
633 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; in rk_udphy_set_typec_default_mapping()
634 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); in rk_udphy_set_typec_default_mapping()
635 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); in rk_udphy_set_typec_default_mapping()
637 udphy->dp_lane_sel[0] = 2; in rk_udphy_set_typec_default_mapping()
638 udphy->dp_lane_sel[1] = 3; in rk_udphy_set_typec_default_mapping()
639 udphy->dp_lane_sel[2] = 1; in rk_udphy_set_typec_default_mapping()
640 udphy->dp_lane_sel[3] = 0; in rk_udphy_set_typec_default_mapping()
641 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; in rk_udphy_set_typec_default_mapping()
642 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; in rk_udphy_set_typec_default_mapping()
643 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; in rk_udphy_set_typec_default_mapping()
644 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; in rk_udphy_set_typec_default_mapping()
645 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; in rk_udphy_set_typec_default_mapping()
646 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; in rk_udphy_set_typec_default_mapping()
647 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); in rk_udphy_set_typec_default_mapping()
648 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); in rk_udphy_set_typec_default_mapping()
651 udphy->mode = UDPHY_MODE_DP_USB; in rk_udphy_set_typec_default_mapping()
659 mutex_lock(&udphy->mutex); in rk_udphy_orien_sw_set()
662 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); in rk_udphy_orien_sw_set()
663 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); in rk_udphy_orien_sw_set()
669 udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; in rk_udphy_orien_sw_set()
674 mutex_unlock(&udphy->mutex); in rk_udphy_orien_sw_set()
682 typec_switch_unregister(udphy->sw); in rk_udphy_orien_switch_unregister()
690 sw_desc.fwnode = dev_fwnode(udphy->dev); in rk_udphy_setup_orien_switch()
693 udphy->sw = typec_switch_register(udphy->dev, &sw_desc); in rk_udphy_setup_orien_switch()
694 if (IS_ERR(udphy->sw)) { in rk_udphy_setup_orien_switch()
695 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", in rk_udphy_setup_orien_switch()
696 PTR_ERR(udphy->sw)); in rk_udphy_setup_orien_switch()
697 return PTR_ERR(udphy->sw); in rk_udphy_setup_orien_switch()
700 return devm_add_action_or_reset(udphy->dev, in rk_udphy_setup_orien_switch()
710 rate = clk_get_rate(udphy->refclk); in rk_udphy_refclk_set()
711 dev_dbg(udphy->dev, "refclk freq %ld\n", rate); in rk_udphy_refclk_set()
715 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, in rk_udphy_refclk_set()
723 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, in rk_udphy_refclk_set()
730 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); in rk_udphy_refclk_set()
731 return -EINVAL; in rk_udphy_refclk_set()
743 if (udphy->mode & UDPHY_MODE_USB) { in rk_udphy_status_check()
744 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, in rk_udphy_status_check()
748 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); in rk_udphy_status_check()
750 * If earlier software (U-Boot) enabled USB once already in rk_udphy_status_check()
753 * time being a -EPROBE_DEFER will solve the issue. in rk_udphy_status_check()
759 return -EPROBE_DEFER; in rk_udphy_status_check()
762 if (!udphy->flip) { in rk_udphy_status_check()
763 ret = regmap_read_poll_timeout(udphy->pma_regmap, in rk_udphy_status_check()
768 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); in rk_udphy_status_check()
770 ret = regmap_read_poll_timeout(udphy->pma_regmap, in rk_udphy_status_check()
775 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); in rk_udphy_status_check()
784 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_init()
791 if (udphy->mode & UDPHY_MODE_USB) in rk_udphy_init()
792 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); in rk_udphy_init()
795 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); in rk_udphy_init()
801 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, in rk_udphy_init()
804 dev_err(udphy->dev, "init sequence set error %d\n", ret); in rk_udphy_init()
810 dev_err(udphy->dev, "refclk set error %d\n", ret); in rk_udphy_init()
815 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, in rk_udphy_init()
817 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | in rk_udphy_init()
818 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | in rk_udphy_init()
819 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | in rk_udphy_init()
820 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | in rk_udphy_init()
824 if (udphy->mode & UDPHY_MODE_USB) in rk_udphy_init()
827 if (udphy->mode & UDPHY_MODE_DP) { in rk_udphy_init()
828 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk_udphy_init()
836 if (udphy->mode & UDPHY_MODE_USB) { in rk_udphy_init()
857 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); in rk_udphy_setup()
859 dev_err(udphy->dev, "failed to enable clk\n"); in rk_udphy_setup()
865 dev_err(udphy->dev, "failed to init combophy\n"); in rk_udphy_setup()
866 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); in rk_udphy_setup()
875 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); in rk_udphy_disable()
883 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); in rk_udphy_parse_lane_mux_data()
885 dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); in rk_udphy_parse_lane_mux_data()
886 udphy->mode = UDPHY_MODE_USB; in rk_udphy_parse_lane_mux_data()
891 return dev_err_probe(udphy->dev, -EINVAL, in rk_udphy_parse_lane_mux_data()
894 ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", in rk_udphy_parse_lane_mux_data()
895 udphy->dp_lane_sel, num_lanes); in rk_udphy_parse_lane_mux_data()
897 return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); in rk_udphy_parse_lane_mux_data()
902 if (udphy->dp_lane_sel[i] > 3) in rk_udphy_parse_lane_mux_data()
903 return dev_err_probe(udphy->dev, -EINVAL, in rk_udphy_parse_lane_mux_data()
906 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; in rk_udphy_parse_lane_mux_data()
909 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) in rk_udphy_parse_lane_mux_data()
910 return dev_err_probe(udphy->dev, -EINVAL, in rk_udphy_parse_lane_mux_data()
915 udphy->mode = UDPHY_MODE_DP; in rk_udphy_parse_lane_mux_data()
917 udphy->mode |= UDPHY_MODE_USB; in rk_udphy_parse_lane_mux_data()
918 udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); in rk_udphy_parse_lane_mux_data()
929 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); in rk_udphy_get_initial_status()
931 dev_err(udphy->dev, "failed to enable clk\n"); in rk_udphy_get_initial_status()
937 regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); in rk_udphy_get_initial_status()
939 udphy->status = UDPHY_MODE_DP; in rk_udphy_get_initial_status()
948 struct device *dev = udphy->dev; in rk_udphy_parse_dt()
953 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); in rk_udphy_parse_dt()
954 if (IS_ERR(udphy->u2phygrf)) in rk_udphy_parse_dt()
955 return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); in rk_udphy_parse_dt()
957 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); in rk_udphy_parse_dt()
958 if (IS_ERR(udphy->udphygrf)) in rk_udphy_parse_dt()
959 return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); in rk_udphy_parse_dt()
961 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); in rk_udphy_parse_dt()
962 if (IS_ERR(udphy->usbgrf)) in rk_udphy_parse_dt()
963 return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); in rk_udphy_parse_dt()
965 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); in rk_udphy_parse_dt()
966 if (IS_ERR(udphy->vogrf)) in rk_udphy_parse_dt()
967 return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); in rk_udphy_parse_dt()
973 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); in rk_udphy_parse_dt()
974 if (IS_ERR(udphy->sbu1_dc_gpio)) in rk_udphy_parse_dt()
975 return PTR_ERR(udphy->sbu1_dc_gpio); in rk_udphy_parse_dt()
977 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); in rk_udphy_parse_dt()
978 if (IS_ERR(udphy->sbu2_dc_gpio)) in rk_udphy_parse_dt()
979 return PTR_ERR(udphy->sbu2_dc_gpio); in rk_udphy_parse_dt()
981 if (device_property_present(dev, "maximum-speed")) { in rk_udphy_parse_dt()
983 udphy->hs = maximum_speed <= USB_SPEED_HIGH; in rk_udphy_parse_dt()
997 if (!(udphy->mode & mode)) { in rk_udphy_power_on()
998 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); in rk_udphy_power_on()
1002 if (udphy->status == UDPHY_MODE_NONE) { in rk_udphy_power_on()
1003 udphy->mode_change = false; in rk_udphy_power_on()
1008 if (udphy->mode & UDPHY_MODE_USB) in rk_udphy_power_on()
1010 } else if (udphy->mode_change) { in rk_udphy_power_on()
1011 udphy->mode_change = false; in rk_udphy_power_on()
1012 udphy->status = UDPHY_MODE_NONE; in rk_udphy_power_on()
1013 if (udphy->mode == UDPHY_MODE_DP) in rk_udphy_power_on()
1022 udphy->status |= mode; in rk_udphy_power_on()
1029 if (!(udphy->mode & mode)) { in rk_udphy_power_off()
1030 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); in rk_udphy_power_off()
1034 if (!udphy->status) in rk_udphy_power_off()
1037 udphy->status &= ~mode; in rk_udphy_power_off()
1039 if (udphy->status == UDPHY_MODE_NONE) in rk_udphy_power_off()
1047 mutex_lock(&udphy->mutex); in rk_udphy_dp_phy_init()
1049 udphy->dp_in_use = true; in rk_udphy_dp_phy_init()
1051 mutex_unlock(&udphy->mutex); in rk_udphy_dp_phy_init()
1060 mutex_lock(&udphy->mutex); in rk_udphy_dp_phy_exit()
1061 udphy->dp_in_use = false; in rk_udphy_dp_phy_exit()
1062 mutex_unlock(&udphy->mutex); in rk_udphy_dp_phy_exit()
1071 mutex_lock(&udphy->mutex); in rk_udphy_dp_phy_power_on()
1085 mutex_unlock(&udphy->mutex); in rk_udphy_dp_phy_power_on()
1099 mutex_lock(&udphy->mutex); in rk_udphy_dp_phy_power_off()
1102 mutex_unlock(&udphy->mutex); in rk_udphy_dp_phy_power_off()
1113 switch (dp->link_rate) { in rk_udphy_dp_phy_verify_link_rate()
1118 udphy->link_rate = dp->link_rate; in rk_udphy_dp_phy_verify_link_rate()
1121 return -EINVAL; in rk_udphy_dp_phy_verify_link_rate()
1130 switch (dp->lanes) { in rk_udphy_dp_phy_verify_lanes()
1135 udphy->lanes = dp->lanes; in rk_udphy_dp_phy_verify_lanes()
1139 return -EINVAL; in rk_udphy_dp_phy_verify_lanes()
1146 * If changing voltages is required, check swing and pre-emphasis
1147 * levels, per-lane.
1155 for (i = 0; i < udphy->lanes; i++) { in rk_udphy_dp_phy_verify_voltages()
1156 if (dp->voltage[i] > 3 || dp->pre[i] > 3) in rk_udphy_dp_phy_verify_voltages()
1157 return -EINVAL; in rk_udphy_dp_phy_verify_voltages()
1160 * Sum of voltage swing and pre-emphasis levels cannot in rk_udphy_dp_phy_verify_voltages()
1163 if (dp->voltage[i] + dp->pre[i] > 3) in rk_udphy_dp_phy_verify_voltages()
1164 return -EINVAL; in rk_udphy_dp_phy_verify_voltages()
1171 u32 voltage, u32 pre, u32 lane) in rk_udphy_dp_set_voltage() argument
1173 const struct rk_udphy_cfg *cfg = udphy->cfgs; in rk_udphy_dp_set_voltage()
1178 if (udphy->mux) in rk_udphy_dp_set_voltage()
1179 dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; in rk_udphy_dp_set_voltage()
1181 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; in rk_udphy_dp_set_voltage()
1183 val = dp_ctrl[voltage][pre].trsv_reg0204; in rk_udphy_dp_set_voltage()
1184 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); in rk_udphy_dp_set_voltage()
1186 val = dp_ctrl[voltage][pre].trsv_reg0205; in rk_udphy_dp_set_voltage()
1187 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); in rk_udphy_dp_set_voltage()
1189 val = dp_ctrl[voltage][pre].trsv_reg0206; in rk_udphy_dp_set_voltage()
1190 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); in rk_udphy_dp_set_voltage()
1192 val = dp_ctrl[voltage][pre].trsv_reg0207; in rk_udphy_dp_set_voltage()
1193 regmap_write(udphy->pma_regmap, 0x081c + offset, val); in rk_udphy_dp_set_voltage()
1200 struct phy_configure_opts_dp *dp = &opts->dp; in rk_udphy_dp_phy_configure()
1204 if (dp->set_rate) { in rk_udphy_dp_phy_configure()
1210 if (dp->set_lanes) { in rk_udphy_dp_phy_configure()
1216 if (dp->set_voltages) { in rk_udphy_dp_phy_configure()
1222 if (dp->set_rate) { in rk_udphy_dp_phy_configure()
1223 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk_udphy_dp_phy_configure()
1226 switch (dp->link_rate) { in rk_udphy_dp_phy_configure()
1228 udphy->bw = DP_BW_RBR; in rk_udphy_dp_phy_configure()
1232 udphy->bw = DP_BW_HBR; in rk_udphy_dp_phy_configure()
1236 udphy->bw = DP_BW_HBR2; in rk_udphy_dp_phy_configure()
1240 udphy->bw = DP_BW_HBR3; in rk_udphy_dp_phy_configure()
1244 return -EINVAL; in rk_udphy_dp_phy_configure()
1247 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, in rk_udphy_dp_phy_configure()
1248 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); in rk_udphy_dp_phy_configure()
1249 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, in rk_udphy_dp_phy_configure()
1250 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); in rk_udphy_dp_phy_configure()
1251 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, in rk_udphy_dp_phy_configure()
1254 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, in rk_udphy_dp_phy_configure()
1259 dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); in rk_udphy_dp_phy_configure()
1264 if (dp->set_voltages) { in rk_udphy_dp_phy_configure()
1265 for (i = 0; i < udphy->lanes; i++) { in rk_udphy_dp_phy_configure()
1266 lane = udphy->dp_lane_sel[i]; in rk_udphy_dp_phy_configure()
1267 switch (udphy->link_rate) { in rk_udphy_dp_phy_configure()
1270 regmap_update_bits(udphy->pma_regmap, in rk_udphy_dp_phy_configure()
1274 udphy->lane_mux_sel[lane])); in rk_udphy_dp_phy_configure()
1279 regmap_update_bits(udphy->pma_regmap, in rk_udphy_dp_phy_configure()
1286 rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], in rk_udphy_dp_phy_configure()
1287 dp->pre[i], lane); in rk_udphy_dp_phy_configure()
1308 mutex_lock(&udphy->mutex); in rk_udphy_usb3_phy_init()
1309 /* DP only or high-speed, disable U3 port */ in rk_udphy_usb3_phy_init()
1310 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { in rk_udphy_usb3_phy_init()
1318 mutex_unlock(&udphy->mutex); in rk_udphy_usb3_phy_init()
1326 mutex_lock(&udphy->mutex); in rk_udphy_usb3_phy_exit()
1327 /* DP only or high-speed */ in rk_udphy_usb3_phy_exit()
1328 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) in rk_udphy_usb3_phy_exit()
1334 mutex_unlock(&udphy->mutex); in rk_udphy_usb3_phy_exit()
1350 mutex_lock(&udphy->mutex); in rk_udphy_typec_mux_set()
1352 switch (state->mode) { in rk_udphy_typec_mux_set()
1355 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1356 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1357 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1358 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1364 if (udphy->flip) { in rk_udphy_typec_mux_set()
1365 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1366 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1367 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; in rk_udphy_typec_mux_set()
1368 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; in rk_udphy_typec_mux_set()
1370 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; in rk_udphy_typec_mux_set()
1371 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; in rk_udphy_typec_mux_set()
1372 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1373 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1379 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { in rk_udphy_typec_mux_set()
1380 struct typec_displayport_data *data = state->data; in rk_udphy_typec_mux_set()
1384 } else if (data->status & DP_STATUS_IRQ_HPD) { in rk_udphy_typec_mux_set()
1388 } else if (data->status & DP_STATUS_HPD_STATE) { in rk_udphy_typec_mux_set()
1389 if (udphy->mode != mode) { in rk_udphy_typec_mux_set()
1390 udphy->mode = mode; in rk_udphy_typec_mux_set()
1391 udphy->mode_change = true; in rk_udphy_typec_mux_set()
1399 mutex_unlock(&udphy->mutex); in rk_udphy_typec_mux_set()
1407 typec_mux_unregister(udphy->mux); in rk_udphy_typec_mux_unregister()
1415 mux_desc.fwnode = dev_fwnode(udphy->dev); in rk_udphy_setup_typec_mux()
1418 udphy->mux = typec_mux_register(udphy->dev, &mux_desc); in rk_udphy_setup_typec_mux()
1419 if (IS_ERR(udphy->mux)) { in rk_udphy_setup_typec_mux()
1420 dev_err(udphy->dev, "Error register typec mux: %ld\n", in rk_udphy_setup_typec_mux()
1421 PTR_ERR(udphy->mux)); in rk_udphy_setup_typec_mux()
1422 return PTR_ERR(udphy->mux); in rk_udphy_setup_typec_mux()
1425 return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, in rk_udphy_setup_typec_mux()
1441 if (args->args_count == 0) in rk_udphy_phy_xlate()
1442 return ERR_PTR(-EINVAL); in rk_udphy_phy_xlate()
1444 switch (args->args[0]) { in rk_udphy_phy_xlate()
1446 return udphy->phy_u3; in rk_udphy_phy_xlate()
1448 return udphy->phy_dp; in rk_udphy_phy_xlate()
1451 return ERR_PTR(-EINVAL); in rk_udphy_phy_xlate()
1456 struct device *dev = &pdev->dev; in rk_udphy_probe()
1465 return -ENOMEM; in rk_udphy_probe()
1467 udphy->cfgs = device_get_match_data(dev); in rk_udphy_probe()
1468 if (!udphy->cfgs) in rk_udphy_probe()
1469 return dev_err_probe(dev, -EINVAL, "missing match data\n"); in rk_udphy_probe()
1475 /* find the phy-id from the io address */ in rk_udphy_probe()
1476 udphy->id = -ENODEV; in rk_udphy_probe()
1477 for (id = 0; id < udphy->cfgs->num_phys; id++) { in rk_udphy_probe()
1478 if (res->start == udphy->cfgs->phy_ids[id]) { in rk_udphy_probe()
1479 udphy->id = id; in rk_udphy_probe()
1484 if (udphy->id < 0) in rk_udphy_probe()
1485 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); in rk_udphy_probe()
1487 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, in rk_udphy_probe()
1489 if (IS_ERR(udphy->pma_regmap)) in rk_udphy_probe()
1490 return PTR_ERR(udphy->pma_regmap); in rk_udphy_probe()
1492 udphy->dev = dev; in rk_udphy_probe()
1501 mutex_init(&udphy->mutex); in rk_udphy_probe()
1504 if (device_property_present(dev, "orientation-switch")) { in rk_udphy_probe()
1510 if (device_property_present(dev, "mode-switch")) { in rk_udphy_probe()
1516 udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); in rk_udphy_probe()
1517 if (IS_ERR(udphy->phy_u3)) { in rk_udphy_probe()
1518 ret = PTR_ERR(udphy->phy_u3); in rk_udphy_probe()
1521 phy_set_drvdata(udphy->phy_u3, udphy); in rk_udphy_probe()
1523 udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); in rk_udphy_probe()
1524 if (IS_ERR(udphy->phy_dp)) { in rk_udphy_probe()
1525 ret = PTR_ERR(udphy->phy_dp); in rk_udphy_probe()
1528 phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); in rk_udphy_probe()
1529 udphy->phy_dp->attrs.max_link_rate = 8100; in rk_udphy_probe()
1530 phy_set_drvdata(udphy->phy_dp, udphy); in rk_udphy_probe()
1545 if (udphy->dp_sink_hpd_sel) in rk_udphy_resume()
1546 rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); in rk_udphy_resume()
1565 /* u2phy-grf */
1569 /* usb-grf */
1572 /* usbdpphy-grf */
1605 /* u2phy-grf */
1609 /* usb-grf */
1613 /* usbdpphy-grf */
1643 .compatible = "rockchip,rk3576-usbdp-phy",
1647 .compatible = "rockchip,rk3588-usbdp-phy",
1657 .name = "rockchip-usbdp-phy",
1664 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1665 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");