Lines Matching +full:0 +full:x42
29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
61 #define CMN_ANA_ROPLL_AFC_DONE BIT(0)
63 #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
67 #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
69 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
72 #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
73 #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
75 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
76 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
79 #define PHY_AUX_DP_DATA_POL_NORMAL 0
81 #define PHY_LANE_MUX_USB 0
92 UDPHY_MODE_NONE = 0,
93 UDPHY_MODE_USB = BIT(0),
95 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
206 /* voltage swing 0, pre-emphasis 0->3 */
208 { 0x20, 0x10, 0x42, 0xe5 },
209 { 0x26, 0x14, 0x42, 0xe5 },
210 { 0x29, 0x18, 0x42, 0xe5 },
211 { 0x2b, 0x1c, 0x43, 0xe7 },
214 /* voltage swing 1, pre-emphasis 0->2 */
216 { 0x23, 0x10, 0x42, 0xe7 },
217 { 0x2a, 0x17, 0x43, 0xe7 },
218 { 0x2b, 0x1a, 0x43, 0xe7 },
221 /* voltage swing 2, pre-emphasis 0->1 */
223 { 0x27, 0x10, 0x42, 0xe7 },
224 { 0x2b, 0x17, 0x43, 0xe7 },
227 /* voltage swing 3, pre-emphasis 0 */
229 { 0x29, 0x10, 0x43, 0xe7 },
234 /* voltage swing 0, pre-emphasis 0->3 */
236 { 0x20, 0x10, 0x42, 0xe5 },
237 { 0x26, 0x14, 0x42, 0xe5 },
238 { 0x29, 0x18, 0x42, 0xe5 },
239 { 0x2b, 0x1c, 0x43, 0xe7 },
242 /* voltage swing 1, pre-emphasis 0->2 */
244 { 0x23, 0x10, 0x42, 0xe7 },
245 { 0x2a, 0x17, 0x43, 0xe7 },
246 { 0x2b, 0x1a, 0x43, 0xe7 },
249 /* voltage swing 2, pre-emphasis 0->1 */
251 { 0x27, 0x10, 0x43, 0x67 },
252 { 0x2b, 0x17, 0x43, 0xe7 },
255 /* voltage swing 3, pre-emphasis 0 */
257 { 0x29, 0x10, 0x43, 0xe7 },
262 /* voltage swing 0, pre-emphasis 0->3 */
264 { 0x21, 0x10, 0x42, 0xe5 },
265 { 0x26, 0x14, 0x42, 0xe5 },
266 { 0x26, 0x16, 0x43, 0xe5 },
267 { 0x2a, 0x19, 0x43, 0xe7 },
270 /* voltage swing 1, pre-emphasis 0->2 */
272 { 0x24, 0x10, 0x42, 0xe7 },
273 { 0x2a, 0x17, 0x43, 0xe7 },
274 { 0x2b, 0x1a, 0x43, 0xe7 },
277 /* voltage swing 2, pre-emphasis 0->1 */
279 { 0x28, 0x10, 0x42, 0xe7 },
280 { 0x2b, 0x17, 0x43, 0xe7 },
283 /* voltage swing 3, pre-emphasis 0 */
285 { 0x28, 0x10, 0x43, 0xe7 },
290 /* voltage swing 0, pre-emphasis 0->3 */
292 { 0x21, 0x10, 0x42, 0xe5 },
293 { 0x26, 0x14, 0x42, 0xe5 },
294 { 0x26, 0x16, 0x43, 0xe5 },
295 { 0x29, 0x18, 0x43, 0xe7 },
298 /* voltage swing 1, pre-emphasis 0->2 */
300 { 0x24, 0x10, 0x42, 0xe7 },
301 { 0x2a, 0x18, 0x43, 0xe7 },
302 { 0x2b, 0x1b, 0x43, 0xe7 }
305 /* voltage swing 2, pre-emphasis 0->1 */
307 { 0x27, 0x10, 0x42, 0xe7 },
308 { 0x2b, 0x18, 0x43, 0xe7 }
311 /* voltage swing 3, pre-emphasis 0 */
313 { 0x28, 0x10, 0x43, 0xe7 },
318 {0x0090, 0x68}, {0x0094, 0x68},
319 {0x0128, 0x24}, {0x012c, 0x44},
320 {0x0130, 0x3f}, {0x0134, 0x44},
321 {0x015c, 0xa9}, {0x0160, 0x71},
322 {0x0164, 0x71}, {0x0168, 0xa9},
323 {0x0174, 0xa9}, {0x0178, 0x71},
324 {0x017c, 0x71}, {0x0180, 0xa9},
325 {0x018c, 0x41}, {0x0190, 0x00},
326 {0x0194, 0x05}, {0x01ac, 0x2a},
327 {0x01b0, 0x17}, {0x01b4, 0x17},
328 {0x01b8, 0x2a}, {0x01c8, 0x04},
329 {0x01cc, 0x08}, {0x01d0, 0x08},
330 {0x01d4, 0x04}, {0x01d8, 0x20},
331 {0x01dc, 0x01}, {0x01e0, 0x09},
332 {0x01e4, 0x03}, {0x01f0, 0x29},
333 {0x01f4, 0x02}, {0x01f8, 0x02},
334 {0x01fc, 0x29}, {0x0208, 0x2a},
335 {0x020c, 0x17}, {0x0210, 0x17},
336 {0x0214, 0x2a}, {0x0224, 0x20},
337 {0x03f0, 0x0a}, {0x03f4, 0x07},
338 {0x03f8, 0x07}, {0x03fc, 0x0c},
339 {0x0404, 0x12}, {0x0408, 0x1a},
340 {0x040c, 0x1a}, {0x0410, 0x3f},
341 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
342 {0x0cf0, 0x87}, {0x0cf8, 0x70},
343 {0x0d00, 0x70}, {0x0d08, 0xa9},
344 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
345 {0x1cf0, 0x87}, {0x1cf8, 0x70},
346 {0x1d00, 0x70}, {0x1d08, 0xa9},
347 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
348 {0x0a48, 0x01}, {0x0a4c, 0x0d},
349 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
350 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
351 {0x1a44, 0xd0}, {0x1a48, 0x01},
352 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
353 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
357 {0x0830, 0x07}, {0x085c, 0x80},
358 {0x1030, 0x07}, {0x105c, 0x80},
359 {0x1830, 0x07}, {0x185c, 0x80},
360 {0x2030, 0x07}, {0x205c, 0x80},
361 {0x0228, 0x38}, {0x0104, 0x44},
362 {0x0248, 0x44}, {0x038c, 0x02},
363 {0x0878, 0x04}, {0x1878, 0x04},
364 {0x0898, 0x77}, {0x1898, 0x77},
365 {0x0054, 0x01}, {0x00e0, 0x38},
366 {0x0060, 0x24}, {0x0064, 0x77},
367 {0x0070, 0x76}, {0x0234, 0xe8},
368 {0x0af4, 0x15}, {0x1af4, 0x15},
369 {0x081c, 0xe5}, {0x181c, 0xe5},
370 {0x099c, 0x48}, {0x199c, 0x48},
371 {0x09a4, 0x07}, {0x09a8, 0x22},
372 {0x19a4, 0x07}, {0x19a8, 0x22},
373 {0x09b8, 0x3e}, {0x19b8, 0x3e},
374 {0x09e4, 0x02}, {0x19e4, 0x02},
375 {0x0a34, 0x1e}, {0x1a34, 0x1e},
376 {0x0a98, 0x2f}, {0x1a98, 0x2f},
377 {0x0c30, 0x0e}, {0x0c48, 0x06},
378 {0x1c30, 0x0e}, {0x1c48, 0x06},
379 {0x028c, 0x18}, {0x0af0, 0x00},
380 {0x1af0, 0x00}
384 {0x0104, 0x44}, {0x0234, 0xe8},
385 {0x0248, 0x44}, {0x028c, 0x18},
386 {0x081c, 0xe5}, {0x0878, 0x00},
387 {0x0994, 0x1c}, {0x0af0, 0x00},
388 {0x181c, 0xe5}, {0x1878, 0x00},
389 {0x1994, 0x1c}, {0x1af0, 0x00},
390 {0x0428, 0x60}, {0x0d58, 0x33},
391 {0x1d58, 0x33}, {0x0990, 0x74},
392 {0x0d64, 0x17}, {0x08c8, 0x13},
393 {0x1990, 0x74}, {0x1d64, 0x17},
394 {0x18c8, 0x13}, {0x0d90, 0x40},
395 {0x0da8, 0x40}, {0x0dc0, 0x40},
396 {0x0dd8, 0x40}, {0x1d90, 0x40},
397 {0x1da8, 0x40}, {0x1dc0, 0x40},
398 {0x1dd8, 0x40}, {0x03c0, 0x30},
399 {0x03c4, 0x06}, {0x0e10, 0x00},
400 {0x1e10, 0x00}, {0x043c, 0x0f},
401 {0x0d2c, 0xff}, {0x1d2c, 0xff},
402 {0x0d34, 0x0f}, {0x1d34, 0x0f},
403 {0x08fc, 0x2a}, {0x0914, 0x28},
404 {0x0a30, 0x03}, {0x0e38, 0x03},
405 {0x0ecc, 0x27}, {0x0ed0, 0x22},
406 {0x0ed4, 0x26}, {0x18fc, 0x2a},
407 {0x1914, 0x28}, {0x1a30, 0x03},
408 {0x1e38, 0x03}, {0x1ecc, 0x27},
409 {0x1ed0, 0x22}, {0x1ed4, 0x26},
410 {0x0048, 0x0f}, {0x0060, 0x3c},
411 {0x0064, 0xf7}, {0x006c, 0x20},
412 {0x0070, 0x7d}, {0x0074, 0x68},
413 {0x0af4, 0x1a}, {0x1af4, 0x1a},
414 {0x0440, 0x3f}, {0x10d4, 0x08},
415 {0x20d4, 0x08}, {0x00d4, 0x30},
416 {0x0024, 0x6e},
434 for (i = 0; i < udphy->num_clks; i++) { in rk_udphy_clk_init()
444 return 0; in rk_udphy_clk_init()
462 for (idx = 0; idx < udphy->num_rsts; idx++) { in rk_udphy_reset_deassert()
481 for (idx = 0; idx < cfg->num_rsts; idx++) in rk_udphy_reset_init()
508 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
528 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
529 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
536 * <0 1> dpln0 dpln1 usbrx usbtx
544 u32 value = 0; in rk_udphy_dplane_select()
553 value |= 0 << udphy->dp_lane_sel[0] * 2; in rk_udphy_dplane_select()
585 dp_lanes = 0; in rk_udphy_dplane_get()
594 u32 val = 0; in rk_udphy_dplane_enable()
597 for (i = 0; i < dp_lanes; i++) in rk_udphy_dplane_enable()
605 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); in rk_udphy_dplane_enable()
624 udphy->dp_lane_sel[0] = 0; in rk_udphy_set_typec_default_mapping()
628 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_set_typec_default_mapping()
635 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); in rk_udphy_set_typec_default_mapping()
637 udphy->dp_lane_sel[0] = 2; in rk_udphy_set_typec_default_mapping()
640 udphy->dp_lane_sel[3] = 0; in rk_udphy_set_typec_default_mapping()
641 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; in rk_udphy_set_typec_default_mapping()
647 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); in rk_udphy_set_typec_default_mapping()
662 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); in rk_udphy_orien_sw_set()
663 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); in rk_udphy_orien_sw_set()
675 return 0; in rk_udphy_orien_sw_set()
734 return 0; in rk_udphy_refclk_set()
779 return 0; in rk_udphy_status_check()
820 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | in rk_udphy_init()
821 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); in rk_udphy_init()
830 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); in rk_udphy_init()
846 return 0; in rk_udphy_init()
870 return 0; in rk_udphy_setup()
884 if (num_lanes < 0) { in rk_udphy_parse_lane_mux_data()
887 return 0; in rk_udphy_parse_lane_mux_data()
899 for (i = 0; i < num_lanes; i++) { in rk_udphy_parse_lane_mux_data()
904 "lane mux between 0 and 3, exceeding the range\n"); in rk_udphy_parse_lane_mux_data()
918 udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); in rk_udphy_parse_lane_mux_data()
921 return 0; in rk_udphy_parse_lane_mux_data()
943 return 0; in rk_udphy_get_initial_status()
998 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); in rk_udphy_power_on()
999 return 0; in rk_udphy_power_on()
1024 return 0; in rk_udphy_power_on()
1030 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); in rk_udphy_power_off()
1053 return 0; in rk_udphy_dp_phy_init()
1063 return 0; in rk_udphy_dp_phy_exit()
1100 rk_udphy_dplane_enable(udphy, 0); in rk_udphy_dp_phy_power_off()
1104 return 0; in rk_udphy_dp_phy_power_off()
1124 return 0; in rk_udphy_dp_phy_verify_link_rate()
1142 return 0; in rk_udphy_dp_phy_verify_lanes()
1155 for (i = 0; i < udphy->lanes; i++) { in rk_udphy_dp_phy_verify_voltages()
1167 return 0; in rk_udphy_dp_phy_verify_voltages()
1175 u32 offset = 0x800 * lane; in rk_udphy_dp_set_voltage()
1184 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); in rk_udphy_dp_set_voltage()
1187 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); in rk_udphy_dp_set_voltage()
1190 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); in rk_udphy_dp_set_voltage()
1193 regmap_write(udphy->pma_regmap, 0x081c + offset, val); in rk_udphy_dp_set_voltage()
1224 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); in rk_udphy_dp_phy_configure()
1252 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); in rk_udphy_dp_phy_configure()
1257 0, 1000); in rk_udphy_dp_phy_configure()
1265 for (i = 0; i < udphy->lanes; i++) { in rk_udphy_dp_phy_configure()
1282 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); in rk_udphy_dp_phy_configure()
1291 return 0; in rk_udphy_dp_phy_configure()
1306 int ret = 0; in rk_udphy_usb3_phy_init()
1335 return 0; in rk_udphy_usb3_phy_exit()
1355 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1365 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in rk_udphy_typec_mux_set()
1370 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; in rk_udphy_typec_mux_set()
1400 return 0; in rk_udphy_typec_mux_set()
1434 .max_register = 0x20dc,
1441 if (args->args_count == 0) in rk_udphy_phy_xlate()
1444 switch (args->args[0]) { in rk_udphy_phy_xlate()
1471 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rk_udphy_probe()
1477 for (id = 0; id < udphy->cfgs->num_phys; id++) { in rk_udphy_probe()
1484 if (udphy->id < 0) in rk_udphy_probe()
1538 return 0; in rk_udphy_probe()
1548 return 0; in rk_udphy_resume()
1561 .phy_ids = { 0x2b010000 },
1566 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3),
1567 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3),
1570 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188),
1573 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
1574 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
1578 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
1579 .dp_lane_reg = 0x0000,
1599 0xfed80000,
1600 0xfed90000,
1606 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3),
1607 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3),
1610 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188),
1611 .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188),
1614 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
1615 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
1619 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
1620 .dp_lane_reg = 0x0000,
1623 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
1624 .dp_lane_reg = 0x0008,