1 // SPDX-License-Identifier: GPL-2.0+
5  *      Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
29 #define BIAS_CON0		0x0000
32 #define I_RES_059_2UA		I_RES_CNTL(0)
40 #define I_DEV_SEL_MASK		GENMASK(1, 0)
42 #define I_DEV_DIV_6		I_DEV_SEL(0)
47 #define BIAS_CON1		0x0004
50 #define I_VBG_SEL_780MV		I_VBG_SEL(0)
56 #define I_BGR_VREF_810MV	I_BGR_VREF_SEL(0)
60 #define I_LADDER_SEL_MASK	GENMASK(2, 0)
62 #define I_LADDER_1_00V		I_LADDER_SEL(0)
73  * The selection between the 400-based or 200-based values for REG_400M
76 #define BIAS_CON2		0x0008
79 #define REG_325M_295MV		REG_325M(0)
89 #define REG_LP_400M_380MV	REG_LP_400M(0)
99 #define REG_400M_380MV		REG_400M(0)
107 #define REG_400M_230MV		REG_400M(0)
115 #define REG_645M_MASK		GENMASK(2, 0)
117 #define REG_645M_605MV		REG_645M(0)
126 #define BIAS_CON4		0x0010
129 #define I_MUX_400MV		I_MUX_SEL(0)
133 #define PLL_CON0		0x0100
137 #define P_MASK			GENMASK(5, 0)
139 #define PLL_CON1		0x0104
140 #define PLL_CON2		0x0108
141 #define M_MASK			GENMASK(9, 0)
143 #define PLL_CON3		0x010c
146 #define MFR_MASK		GENMASK(7, 0)
148 #define PLL_CON4		0x0110
150 #define PLL_CON5		0x0114
153 #define PLL_CON6		0x0118
154 #define PLL_CON7		0x011c
155 #define PLL_LOCK_CNT(x)		FIELD_PREP(GENMASK(15, 0), x)
156 #define PLL_CON8		0x0120
157 #define PLL_STB_CNT(x)		FIELD_PREP(GENMASK(15, 0), x)
158 #define PLL_STAT0		0x0140
159 #define PLL_LOCK		BIT(0)
161 #define DPHY_MC_GNR_CON0	0x0300
163 #define PHY_ENABLE		BIT(0)
164 #define DPHY_MC_GNR_CON1	0x0304
165 #define T_PHY_READY(x)		FIELD_PREP(GENMASK(15, 0), x)
166 #define DPHY_MC_ANA_CON0	0x0308
171 #define RES_DN(x)		FIELD_PREP(GENMASK(3, 0), x)
172 #define DPHY_MC_ANA_CON1	0x030c
173 #define DPHY_MC_ANA_CON2	0x0310
174 #define HS_VREG_AMP_ICON(x)	FIELD_PREP(GENMASK(1, 0), x)
175 #define DPHY_MC_TIME_CON0	0x0330
178 #define DPHY_MC_TIME_CON1	0x0334
179 #define T_CLK_ZERO(x)		FIELD_PREP(GENMASK(15, 8), x)
180 #define T_CLK_PREPARE(x)	FIELD_PREP(GENMASK(7, 0), x)
181 #define DPHY_MC_TIME_CON2	0x0338
182 #define T_HS_EXIT(x)		FIELD_PREP(GENMASK(15, 8), x)
183 #define T_CLK_TRAIL(x)		FIELD_PREP(GENMASK(7, 0), x)
184 #define DPHY_MC_TIME_CON3	0x033c
185 #define T_CLK_POST(x)		FIELD_PREP(GENMASK(7, 0), x)
186 #define DPHY_MC_TIME_CON4	0x0340
187 #define T_ULPS_EXIT(x)		FIELD_PREP(GENMASK(9, 0), x)
188 #define DPHY_MC_DESKEW_CON0	0x0350
189 #define SKEW_CAL_RUN_TIME(x)	FIELD_PREP(GENMASK(15, 12), x)
193 #define SKEW_CAL_EN			BIT(0)
195 #define COMBO_MD0_GNR_CON0	0x0400
196 #define COMBO_MD0_GNR_CON1	0x0404
197 #define COMBO_MD0_ANA_CON0	0x0408
198 #define COMBO_MD0_ANA_CON1	0x040c
199 #define COMBO_MD0_ANA_CON2	0x0410
201 #define COMBO_MD0_TIME_CON0	0x0430
202 #define COMBO_MD0_TIME_CON1	0x0434
203 #define COMBO_MD0_TIME_CON2	0x0438
204 #define COMBO_MD0_TIME_CON3	0x043c
205 #define COMBO_MD0_TIME_CON4	0x0440
206 #define COMBO_MD0_DATA_CON0	0x0444
208 #define COMBO_MD1_GNR_CON0	0x0500
209 #define COMBO_MD1_GNR_CON1	0x0504
210 #define COMBO_MD1_ANA_CON0	0x0508
211 #define COMBO_MD1_ANA_CON1	0x050c
212 #define COMBO_MD1_ANA_CON2	0x0510
213 #define COMBO_MD1_TIME_CON0	0x0530
214 #define COMBO_MD1_TIME_CON1	0x0534
215 #define COMBO_MD1_TIME_CON2	0x0538
216 #define COMBO_MD1_TIME_CON3	0x053c
217 #define COMBO_MD1_TIME_CON4	0x0540
218 #define COMBO_MD1_DATA_CON0	0x0544
220 #define COMBO_MD2_GNR_CON0	0x0600
221 #define COMBO_MD2_GNR_CON1	0x0604
222 #define COMBO_MD2_ANA_CON0	0X0608
223 #define COMBO_MD2_ANA_CON1	0X060c
224 #define COMBO_MD2_ANA_CON2	0X0610
225 #define COMBO_MD2_TIME_CON0	0x0630
226 #define COMBO_MD2_TIME_CON1	0x0634
227 #define COMBO_MD2_TIME_CON2	0x0638
228 #define COMBO_MD2_TIME_CON3	0x063c
229 #define COMBO_MD2_TIME_CON4	0x0640
230 #define COMBO_MD2_DATA_CON0	0x0644
232 #define DPHY_MD3_GNR_CON0	0x0700
233 #define DPHY_MD3_GNR_CON1	0x0704
234 #define DPHY_MD3_ANA_CON0	0X0708
235 #define DPHY_MD3_ANA_CON1	0X070c
236 #define DPHY_MD3_ANA_CON2	0X0710
237 #define DPHY_MD3_TIME_CON0	0x0730
238 #define DPHY_MD3_TIME_CON1	0x0734
239 #define DPHY_MD3_TIME_CON2	0x0738
240 #define DPHY_MD3_TIME_CON3	0x073c
241 #define DPHY_MD3_TIME_CON4	0x0740
242 #define DPHY_MD3_DATA_CON0	0x0744
245 #define T_LP_ENTRY_SKEW(x)	FIELD_PREP(GENMASK(1, 0), x)
246 #define T_HS_ZERO(x)		FIELD_PREP(GENMASK(15, 8), x)
247 #define T_HS_PREPARE(x)		FIELD_PREP(GENMASK(7, 0), x)
248 #define T_HS_EXIT(x)		FIELD_PREP(GENMASK(15, 8), x)
249 #define T_HS_TRAIL(x)		FIELD_PREP(GENMASK(7, 0), x)
251 #define T_TA_GO(x)		FIELD_PREP(GENMASK(3, 0), x)
254 #define MIPI_DCPHY_GRF_CON0		0x0000
256 #define M_CPHY_MODE			FIELD_PREP_HIWORD(BIT(0), 1)
259 	STRENGTH_30_OHM = 0x8,
267 	STRENGTH_43_OHM = 0x0,
561 	{4260, 21,  75, 20, 18, 20, 35, 17, 15, 29, 24},
562 	{4250, 20,  76, 20, 18, 20, 35, 17, 15, 29, 24},
563 	{4240, 20,  76, 20, 18, 20, 35, 17, 15, 29, 23},
564 	{4230, 20,  75, 20, 18, 20, 35, 17, 15, 29, 23},
565 	{4220, 20,  75, 20, 18, 20, 35, 17, 15, 29, 23},
566 	{4210, 20,  75, 20, 18, 20, 35, 17, 15, 28, 23},
567 	{4200, 20,  75, 19, 18, 19, 36, 17, 15, 28, 23},
568 	{4190, 20,  74, 19, 18, 19, 36, 17, 15, 28, 23},
569 	{4180, 20,  74, 19, 18, 19, 35, 17, 15, 28, 23},
570 	{4170, 20,  74, 19, 18, 19, 35, 17, 15, 28, 23},
571 	{4160, 20,  74, 19, 18, 19, 35, 17, 15, 28, 23},
572 	{4150, 20,  74, 19, 18, 19, 35, 17, 15, 28, 23},
573 	{4140, 20,  73, 19, 18, 19, 35, 17, 15, 28, 23},
574 	{4130, 20,  73, 19, 18, 19, 35, 17, 15, 28, 23},
575 	{4120, 20,  73, 19, 18, 19, 35, 17, 15, 28, 23},
576 	{4110, 20,  73, 19, 18, 19, 34, 17, 15, 28, 23},
577 	{4100, 20,  72, 19, 18, 19, 34, 17, 15, 28, 23},
578 	{4090, 20,  72, 19, 18, 19, 34, 17, 15, 28, 23},
579 	{4080, 20,  72, 19, 18, 19, 34, 17, 15, 28, 23},
580 	{4070, 20,  72, 19, 18, 19, 34, 17, 15, 27, 22},
581 	{4060, 19,  72, 19, 17, 19, 34, 17, 15, 27, 22},
582 	{4050, 19,  72, 19, 17, 19, 34, 17, 15, 27, 22},
583 	{4040, 19,  72, 19, 17, 19, 33, 17, 15, 27, 22},
584 	{4030, 19,  72, 19, 17, 19, 33, 17, 15, 27, 22},
585 	{4020, 19,  71, 19, 17, 19, 33, 16, 15, 27, 22},
586 	{4010, 19,  71, 19, 17, 19, 33, 16, 15, 27, 22},
608 	{3790, 18,  67, 17, 16, 17, 32, 15, 14, 26, 21},
609 	{3780, 18,  67, 17, 16, 17, 32, 15, 14, 25, 21},
610 	{3770, 18,  67, 17, 16, 17, 32, 15, 14, 25, 21},
611 	{3760, 18,  66, 17, 16, 17, 32, 15, 14, 25, 21},
612 	{3750, 18,  66, 17, 16, 17, 31, 15, 14, 25, 21},
613 	{3740, 18,  66, 17, 16, 17, 31, 15, 14, 25, 20},
614 	{3730, 18,  66, 17, 16, 17, 31, 15, 13, 25, 20},
615 	{3720, 18,  65, 17, 16, 17, 31, 15, 13, 25, 20},
616 	{3710, 18,  65, 17, 16, 17, 31, 15, 13, 25, 20},
617 	{3700, 18,  65, 17, 16, 17, 31, 15, 13, 25, 20},
618 	{3690, 18,  65, 17, 16, 17, 31, 15, 13, 25, 20},
619 	{3680, 18,  64, 17, 16, 17, 31, 15, 13, 25, 20},
620 	{3670, 18,  64, 17, 16, 17, 30, 15, 13, 25, 20},
621 	{3660, 17,  65, 17, 16, 17, 30, 15, 13, 25, 20},
622 	{3650, 17,  65, 17, 16, 17, 30, 15, 13, 25, 20},
623 	{3640, 17,  65, 17, 16, 17, 30, 15, 13, 25, 20},
624 	{3630, 17,  64, 17, 16, 17, 30, 15, 13, 24, 20},
625 	{3620, 17,  64, 17, 16, 17, 30, 15, 13, 24, 20},
626 	{3610, 17,  64, 17, 16, 17, 30, 15, 13, 24, 20},
627 	{3600, 17,  64, 16, 16, 17, 29, 15, 13, 24, 20},
628 	{3590, 17,  63, 16, 15, 17, 29, 15, 13, 24, 20},
629 	{3580, 17,  63, 16, 15, 16, 30, 15, 13, 24, 20},
630 	{3570, 17,  63, 16, 15, 16, 30, 15, 13, 24, 19},
631 	{3560, 17,  63, 16, 15, 16, 30, 14, 13, 24, 19},
632 	{3550, 17,  62, 16, 15, 16, 30, 14, 13, 24, 19},
633 	{3540, 17,  62, 16, 15, 16, 30, 14, 13, 24, 19},
634 	{3530, 17,  62, 16, 15, 16, 29, 14, 13, 24, 19},
635 	{3520, 17,  62, 16, 15, 16, 29, 14, 13, 24, 19},
636 	{3510, 17,  62, 16, 15, 16, 29, 14, 13, 24, 19},
637 	{3500, 17,  61, 16, 15, 16, 29, 14, 13, 24, 19},
638 	{3490, 17,  61, 16, 15, 16, 29, 14, 13, 23, 19},
639 	{3480, 17,  61, 16, 15, 16, 29, 14, 13, 23, 19},
640 	{3470, 17,  61, 16, 15, 16, 29, 14, 13, 23, 19},
641 	{3460, 16,  61, 16, 15, 16, 28, 14, 12, 23, 19},
642 	{3450, 16,  61, 16, 15, 16, 28, 14, 12, 23, 19},
643 	{3440, 16,  61, 16, 15, 16, 28, 14, 12, 23, 19},
644 	{3430, 16,  61, 16, 15, 16, 28, 14, 12, 23, 19},
645 	{3420, 16,  60, 16, 15, 16, 28, 14, 12, 23, 19},
646 	{3410, 16,  60, 16, 15, 16, 28, 14, 12, 23, 18},
647 	{3400, 16,  60, 15, 15, 16, 28, 14, 12, 23, 18},
648 	{3390, 16,  60, 15, 15, 16, 28, 14, 12, 23, 18},
649 	{3380, 16,  59, 15, 15, 16, 27, 14, 12, 23, 18},
650 	{3370, 16,  59, 15, 15, 15, 28, 14, 12, 23, 18},
651 	{3360, 16,  59, 15, 14, 15, 28, 14, 12, 23, 18},
652 	{3350, 16,  59, 15, 14, 15, 28, 14, 12, 23, 18},
653 	{3340, 16,  59, 15, 14, 15, 28, 14, 12, 22, 18},
654 	{3330, 16,  58, 15, 14, 15, 28, 14, 12, 22, 18},
655 	{3320, 16,  58, 15, 14, 15, 28, 13, 12, 22, 18},
656 	{3310, 16,  58, 15, 14, 15, 27, 13, 12, 22, 18},
657 	{3300, 16,  58, 15, 14, 15, 27, 13, 12, 22, 18},
658 	{3290, 16,  57, 15, 14, 15, 27, 13, 12, 22, 18},
659 	{3280, 16,  57, 15, 14, 15, 27, 13, 12, 22, 18},
660 	{3270, 16,  57, 15, 14, 15, 27, 13, 12, 22, 18},
661 	{3260, 15,  58, 15, 14, 15, 27, 13, 12, 22, 18},
662 	{3250, 15,  57, 15, 14, 15, 27, 13, 12, 22, 18},
663 	{3240, 15,  57, 15, 14, 15, 26, 13, 12, 22, 17},
664 	{3230, 15,  57, 15, 14, 15, 26, 13, 12, 22, 17},
665 	{3220, 15,  57, 15, 14, 15, 26, 13, 12, 22, 17},
666 	{3210, 15,  56, 15, 14, 15, 26, 13, 12, 22, 17},
667 	{3200, 15,  56, 14, 14, 15, 26, 13, 11, 21, 17},
668 	{3190, 15,  56, 14, 14, 15, 26, 13, 11, 21, 17},
669 	{3180, 15,  56, 14, 14, 15, 26, 13, 11, 21, 17},
670 	{3170, 15,  56, 14, 14, 15, 25, 13, 11, 21, 17},
671 	{3160, 15,  55, 14, 14, 14, 26, 13, 11, 21, 17},
672 	{3150, 15,  55, 14, 14, 14, 26, 13, 11, 21, 17},
673 	{3140, 15,  55, 14, 14, 14, 26, 13, 11, 21, 17},
674 	{3130, 15,  55, 14, 14, 14, 26, 13, 11, 21, 17},
675 	{3120, 15,  54, 14, 13, 14, 26, 13, 11, 21, 17},
676 	{3110, 15,  54, 14, 13, 14, 26, 13, 11, 21, 17},
677 	{3100, 15,  54, 14, 13, 14, 26, 13, 11, 21, 17},
678 	{3090, 15,  54, 14, 13, 14, 25, 12, 11, 21, 17},
679 	{3080, 15,  53, 14, 13, 14, 25, 12, 11, 21, 17},
696 	{2910, 14,  50, 13, 13, 13, 24, 12, 10, 20, 15},
697 	{2900, 14,  50, 13, 13, 13, 24, 12, 10, 19, 15},
698 	{2890, 14,  50, 13, 12, 13, 24, 12, 10, 19, 15},
699 	{2880, 14,  50, 13, 12, 13, 23, 12, 10, 19, 15},
700 	{2870, 13,  50, 13, 12, 13, 23, 12, 10, 19, 15},
701 	{2860, 13,  50, 13, 12, 13, 23, 12, 10, 19, 15},
702 	{2850, 13,  50, 13, 12, 13, 23, 11, 10, 19, 15},
703 	{2840, 13,  50, 13, 12, 13, 23, 11, 10, 19, 15},
704 	{2830, 13,  50, 13, 12, 13, 23, 11, 10, 19, 15},
705 	{2820, 13,  49, 13, 12, 13, 23, 11, 10, 19, 15},
706 	{2810, 13,  49, 13, 12, 13, 23, 11, 10, 19, 15},
707 	{2800, 13,  49, 12, 12, 13, 22, 11, 10, 19, 15},
708 	{2790, 13,  49, 12, 12, 13, 22, 11, 10, 19, 15},
709 	{2780, 13,  48, 12, 12, 13, 22, 11, 10, 19, 15},
710 	{2770, 13,  48, 12, 12, 13, 22, 11, 10, 19, 15},
711 	{2760, 13,  48, 12, 12, 13, 22, 11, 10, 18, 15},
712 	{2750, 13,  48, 12, 12, 13, 22, 11, 10, 18, 15},
755 	{2320, 11,  40, 10, 10, 10, 19,  9,  8, 15, 12},
756 	{2310, 11,  39, 10, 10, 10, 19,  9,  8, 15, 12},
757 	{2300, 11,  39, 10, 10, 10, 18,  9,  8, 15, 12},
758 	{2290, 11,  39, 10, 10, 10, 18,  9,  8, 15, 12},
759 	{2280, 11,  39, 10, 10, 10, 18,  9,  8, 15, 12},
760 	{2270, 10,  39, 10, 10, 10, 18,  9,  8, 15, 12},
761 	{2260, 10,  39, 10, 10, 10, 18,  9,  8, 15, 12},
762 	{2250, 10,  39, 10, 10, 10, 18,  9,  8, 15, 12},
763 	{2240, 10,  39, 10, 10, 10, 18,  9,  8, 15, 11},
764 	{2230, 10,  38, 10, 10, 10, 18,  9,  8, 15, 11},
765 	{2220, 10,  38, 10, 10, 10, 17,  9,  8, 15, 11},
766 	{2210, 10,  38, 10, 10, 10, 17,  9,  8, 15, 11},
767 	{2200, 10,  38,  9, 10, 10, 17,  9,  8, 15, 11},
768 	{2190, 10,  38,  9,  9, 10, 17,  9,  8, 15, 11},
786 	{2010,  9,  34,  9,  9,  9, 15,  8,  7, 13, 10},
787 	{2000,  9,  34,  8,  9,  9, 15,  8,  7, 13, 10},
788 	{1990,  9,  34,  8,  9,  9, 15,  8,  7, 13, 10},
789 	{1980,  9,  34,  8,  9,  9, 15,  8,  7, 13, 10},
790 	{1970,  9,  33,  8,  9,  9, 15,  8,  7, 13, 10},
791 	{1960,  9,  33,  8,  9,  9, 15,  8,  7, 13, 10},
792 	{1950,  9,  33,  8,  8,  9, 15,  8,  7, 13, 10},
793 	{1940,  9,  33,  8,  8,  9, 15,  8,  7, 13, 10},
796 	{1910,  9,  32,  8,  8,  8, 15,  7,  7, 13,  9},
797 	{1900,  9,  32,  8,  8,  8, 15,  7,  7, 13,  9},
798 	{1890,  9,  31,  8,  8,  8, 15,  7,  7, 12,  9},
799 	{1880,  8,  32,  8,  8,  8, 15,  7,  7, 12,  9},
800 	{1870,  8,  32,  8,  8,  8, 15,  7,  7, 12,  9},
888 	{ 990, 39,  15,  3, 60, 39,  6, 53, 29,  5, 49},
889 	{ 980, 39,  15,  3, 59, 39,  5, 52, 29,  5, 49},
890 	{ 970, 38,  15,  3, 59, 39,  5, 52, 29,  5, 48},
891 	{ 960, 38,  15,  3, 59, 39,  5, 52, 29,  5, 48},
892 	{ 950, 37,  15,  3, 58, 39,  5, 51, 29,  5, 47},
934 	{ 530, 20,   7,  1, 44, 22,  1, 37, 15,  2, 27},
935 	{ 520, 20,   7,  1, 43, 21,  1, 37, 15,  2, 27},
936 	{ 510, 20,   6,  1, 43, 21,  1, 36, 15,  2, 26},
937 	{ 500, 19,   6,  1, 43, 22,  1, 36, 15,  2, 26},
938 	{ 490, 19,   6,  1, 42, 21,  1, 36, 15,  2, 25},
939 	{ 480, 18,   6,  1, 42, 21,  1, 35, 15,  2, 25},
940 	{ 470, 18,   6,  1, 42, 21,  1, 35, 15,  2, 24},
944 	{ 430, 16,   5,  1, 40, 18,  0, 34, 12,  2, 22},
945 	{ 420, 16,   5,  1, 40, 18,  0, 33, 12,  2, 22},
946 	{ 410, 16,   5,  1, 40, 17,  0, 33, 12,  1, 21},
947 	{ 400, 15,   5,  0, 39, 17,  0, 33, 11,  1, 21},
948 	{ 390, 15,   4,  0, 39, 17,  0, 32, 12,  1, 20},
949 	{ 380, 14,   4,  0, 39, 17,  0, 32, 12,  1, 20},
950 	{ 370, 14,   4,  0, 38, 17,  0, 32, 12,  1, 19},
951 	{ 360, 14,   4,  0, 38, 15,  0, 31, 10,  1, 19},
952 	{ 350, 13,   4,  0, 38, 15,  0, 31, 10,  1, 18},
953 	{ 340, 13,   3,  0, 37, 15,  0, 31, 10,  1, 18},
954 	{ 330, 12,   3,  0, 37, 14,  0, 30,  9,  1, 17},
955 	{ 320, 12,   3,  0, 37, 14,  0, 30,  9,  1, 17},
956 	{ 310, 12,   3,  0, 36, 13,  0, 30,  9,  1, 16},
957 	{ 300, 11,   3,  0, 36, 13,  0, 29,  8,  1, 16},
958 	{ 290, 11,   2,  0, 36, 13,  0, 29,  8,  1, 15},
959 	{ 280, 10,   2,  0, 35, 12,  0, 29,  8,  1, 15},
960 	{ 270, 10,   2,  0, 35, 12,  0, 28,  8,  0, 14},
961 	{ 260,  9,   2,  0, 35, 12,  0, 28,  8,  0, 14},
962 	{ 250,  9,   2,  0, 34, 12,  0, 28,  8,  0, 14},
963 	{ 240,  9,   2,  0, 34, 12,  0, 27,  8,  0, 13},
964 	{ 230,  8,   1,  0, 34, 10,  0, 27,  6,  0, 13},
965 	{ 220,  8,   1,  0, 33, 10,  0, 27,  6,  0, 12},
966 	{ 210,  7,   1,  0, 33, 10,  0, 26,  6,  0, 12},
967 	{ 200,  7,   1,  0, 33,  9,  0, 26,  5,  0, 11},
968 	{ 190,  7,   1,  0, 32,  9,  0, 25,  5,  0, 11},
969 	{ 180,  6,   1,  0, 32,  8,  0, 25,  5,  0, 10},
970 	{ 170,  6,   0,  0, 32,  8,  0, 25,  5,  0, 10},
971 	{ 160,  5,   0,  0, 31,  8,  0, 24,  4,  0,  9},
972 	{ 150,  5,   0,  0, 31,  8,  0, 24,  5,  0,  9},
973 	{ 140,  5,   0,  0, 31,  8,  0, 24,  5,  0,  8},
974 	{ 130,  4,   0,  0, 30,  6,  0, 23,  3,  0,  8},
975 	{ 120,  4,   0,  0, 30,  6,  0, 23,  3,  0,  7},
976 	{ 110,  3,   0,  0, 30,  6,  0, 23,  3,  0,  7},
977 	{ 100,  3,   0,  0, 29,  5,  0, 22,  2,  0,  6},
978 	{  90,  3,   0,  0, 29,  5,  0, 22,  2,  0,  6},
979 	{  80,  2,   0,  0, 28,  5,  0, 22,  2,  0,  5},
984 	regmap_write(samsung->regmap, BIAS_CON0, I_DEV_DIV_6 | I_RES_100_2UA);  in samsung_mipi_dcphy_bias_block_enable()
985 	regmap_write(samsung->regmap, BIAS_CON1, I_VBG_SEL_820MV | I_BGR_VREF_820MV |  in samsung_mipi_dcphy_bias_block_enable()
987 	regmap_write(samsung->regmap, BIAS_CON2, REG_325M_325MV | REG_LP_400M_400MV |  in samsung_mipi_dcphy_bias_block_enable()
994 	regmap_update_bits(samsung->regmap, BIAS_CON4,  in samsung_mipi_dcphy_bias_block_enable()
1000 	regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1001 	regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1004 	switch (samsung->lanes) {  in samsung_mipi_dphy_lane_enable()
1006 		regmap_write(samsung->regmap, DPHY_MD3_GNR_CON1,  in samsung_mipi_dphy_lane_enable()
1007 			     T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1008 		regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1012 		regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1,  in samsung_mipi_dphy_lane_enable()
1013 			     T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1014 		regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1018 		regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1,  in samsung_mipi_dphy_lane_enable()
1019 			     T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1020 		regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1025 		regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1,  in samsung_mipi_dphy_lane_enable()
1026 			     T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1027 		regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1035 	switch (samsung->lanes) {  in samsung_mipi_dphy_lane_disable()
1037 		regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0,  in samsung_mipi_dphy_lane_disable()
1038 				   PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1041 		regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0,  in samsung_mipi_dphy_lane_disable()
1042 				   PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1045 		regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0,  in samsung_mipi_dphy_lane_disable()
1046 				   PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1050 		regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0,  in samsung_mipi_dphy_lane_disable()
1051 				   PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1055 	regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1060 	regmap_update_bits(samsung->regmap, PLL_CON0, S_MASK | P_MASK,  in samsung_mipi_dcphy_pll_configure()
1061 			   S(samsung->pll.scaler) | P(samsung->pll.prediv));  in samsung_mipi_dcphy_pll_configure()
1063 	if (samsung->pll.dsm < 0) {  in samsung_mipi_dcphy_pll_configure()
1067 		dsm_tmp = abs(samsung->pll.dsm);  in samsung_mipi_dcphy_pll_configure()
1068 		dsm_tmp = dsm_tmp - 1;  in samsung_mipi_dcphy_pll_configure()
1069 		dsm_tmp ^= 0xffff;  in samsung_mipi_dcphy_pll_configure()
1070 		regmap_write(samsung->regmap, PLL_CON1, dsm_tmp);  in samsung_mipi_dcphy_pll_configure()
1072 		regmap_write(samsung->regmap, PLL_CON1, samsung->pll.dsm);  in samsung_mipi_dcphy_pll_configure()
1075 	regmap_update_bits(samsung->regmap, PLL_CON2,  in samsung_mipi_dcphy_pll_configure()
1076 			   M_MASK, M(samsung->pll.fbdiv));  in samsung_mipi_dcphy_pll_configure()
1078 	if (samsung->pll.ssc_en) {  in samsung_mipi_dcphy_pll_configure()
1079 		regmap_write(samsung->regmap, PLL_CON3,  in samsung_mipi_dcphy_pll_configure()
1080 			     MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr));  in samsung_mipi_dcphy_pll_configure()
1081 		regmap_update_bits(samsung->regmap, PLL_CON4, SSCG_EN, SSCG_EN);  in samsung_mipi_dcphy_pll_configure()
1084 	regmap_write(samsung->regmap, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL);  in samsung_mipi_dcphy_pll_configure()
1085 	regmap_write(samsung->regmap, PLL_CON7, PLL_LOCK_CNT(0xf000));  in samsung_mipi_dcphy_pll_configure()
1086 	regmap_write(samsung->regmap, PLL_CON8, PLL_STB_CNT(0xf000));  in samsung_mipi_dcphy_pll_configure()
1094 	regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, PLL_EN);  in samsung_mipi_dcphy_pll_enable()
1096 	ret = regmap_read_poll_timeout(samsung->regmap, PLL_STAT0,  in samsung_mipi_dcphy_pll_enable()
1098 	if (ret < 0)  in samsung_mipi_dcphy_pll_enable()
1099 		dev_err(samsung->dev, "DC-PHY pll failed to lock\n");  in samsung_mipi_dcphy_pll_enable()
1106 	regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, 0);  in samsung_mipi_dcphy_pll_disable()
1114 	unsigned int lane_mbps = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_dphy_get_timing()
1120 	for (i = num_timings; i > 1; i--)  in samsung_mipi_dphy_get_timing()
1121 		if (lane_mbps <= timings[i - 1].max_lane_mbps)  in samsung_mipi_dphy_get_timing()
1124 	return &timings[i - 1];  in samsung_mipi_dphy_get_timing()
1132 	u32 max_fout = samsung->pdata->dphy_tx_max_lane_kbps;  in samsung_mipi_dcphy_pll_round_rate()
1133 	u64 best_freq = 0;  in samsung_mipi_dcphy_pll_round_rate()
1138 	u8 _scaler, best_scaler = 0;  in samsung_mipi_dcphy_pll_round_rate()
1140 	long _dsm, best_dsm = 0;  in samsung_mipi_dcphy_pll_round_rate()
1143 		dev_err(samsung->dev, "parent rate of PLL can not be zero\n");  in samsung_mipi_dcphy_pll_round_rate()
1144 		return 0;  in samsung_mipi_dcphy_pll_round_rate()
1159 		/* 0 ≤ S[2:0] ≤ 6 */  in samsung_mipi_dcphy_pll_round_rate()
1160 		for (_scaler = 0; _scaler < 7; _scaler++) {  in samsung_mipi_dcphy_pll_round_rate()
1178 				 /* 64 ≤ M[9:0] ≤ 1023 */  in samsung_mipi_dcphy_pll_round_rate()
1182 				/* -32767 ≤ K[15:0] ≤ 32767 */  in samsung_mipi_dcphy_pll_round_rate()
1183 				_dsm = ((_prediv * fvco) - (2 * _fbdiv * fin));  in samsung_mipi_dcphy_pll_round_rate()
1184 				_dsm = DIV_ROUND_UP_ULL(_dsm << 15, fin);  in samsung_mipi_dcphy_pll_round_rate()
1189 				tmp += DIV_ROUND_CLOSEST_ULL((_dsm * fin * 1000), _prediv << 15);  in samsung_mipi_dcphy_pll_round_rate()
1191 				delta = abs(fvco * MSEC_PER_SEC - tmp);  in samsung_mipi_dcphy_pll_round_rate()
1208 	*dsm = (int)best_dsm & 0xffff;  in samsung_mipi_dcphy_pll_round_rate()
1210 	dev_dbg(samsung->dev, "p: %d, m: %d, dsm:%ld, scaler: %d\n",  in samsung_mipi_dcphy_pll_round_rate()
1220 	unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_dphy_clk_lane_timing_init()
1224 	regmap_write(samsung->regmap, DPHY_MC_GNR_CON0, 0xf000);  in samsung_mipi_dphy_clk_lane_timing_init()
1227 	 * The Drive-Strength / Voltage-Amplitude is adjusted by setting  in samsung_mipi_dphy_clk_lane_timing_init()
1228 	 * the Driver-Up Resistor and Driver-Down Resistor.  in samsung_mipi_dphy_clk_lane_timing_init()
1230 	res_up = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_up_ohm;  in samsung_mipi_dphy_clk_lane_timing_init()
1231 	res_down = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_down_ohm;  in samsung_mipi_dphy_clk_lane_timing_init()
1232 	val = EDGE_CON(7) | EDGE_CON_DIR(0) | EDGE_CON_EN |  in samsung_mipi_dphy_clk_lane_timing_init()
1234 	regmap_write(samsung->regmap, DPHY_MC_ANA_CON0, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1237 		regmap_write(samsung->regmap, DPHY_MC_ANA_CON1, 0x0001);  in samsung_mipi_dphy_clk_lane_timing_init()
1239 	val = 0;  in samsung_mipi_dphy_clk_lane_timing_init()
1241 	 * Divide-by-2 Clock from Serial Clock. Use this when data rate is under  in samsung_mipi_dphy_clk_lane_timing_init()
1242 	 * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock  in samsung_mipi_dphy_clk_lane_timing_init()
1247 	val |= T_LPX(timing->lpx);  in samsung_mipi_dphy_clk_lane_timing_init()
1249 	regmap_write(samsung->regmap, DPHY_MC_TIME_CON0, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1251 	val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare);  in samsung_mipi_dphy_clk_lane_timing_init()
1252 	regmap_write(samsung->regmap, DPHY_MC_TIME_CON1, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1254 	val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot);  in samsung_mipi_dphy_clk_lane_timing_init()
1255 	regmap_write(samsung->regmap, DPHY_MC_TIME_CON2, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1257 	val = T_CLK_POST(timing->clk_post);  in samsung_mipi_dphy_clk_lane_timing_init()
1258 	regmap_write(samsung->regmap, DPHY_MC_TIME_CON3, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1261 	regmap_write(samsung->regmap, DPHY_MC_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_clk_lane_timing_init()
1268 		regmap_write(samsung->regmap, DPHY_MC_DESKEW_CON0, 0x9cb1);  in samsung_mipi_dphy_clk_lane_timing_init()
1275 	unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_dphy_data_lane_timing_init()
1281 	 * The Drive-Strength / Voltage-Amplitude is adjusted by adjusting the  in samsung_mipi_dphy_data_lane_timing_init()
1282 	 *  Driver-Up Resistor and Driver-Down Resistor.  in samsung_mipi_dphy_data_lane_timing_init()
1284 	res_up = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_up_ohm;  in samsung_mipi_dphy_data_lane_timing_init()
1285 	res_down = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_down_ohm;  in samsung_mipi_dphy_data_lane_timing_init()
1286 	val = EDGE_CON(7) | EDGE_CON_DIR(0) | EDGE_CON_EN |  in samsung_mipi_dphy_data_lane_timing_init()
1288 	regmap_write(samsung->regmap, COMBO_MD0_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1289 	regmap_write(samsung->regmap, COMBO_MD1_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1290 	regmap_write(samsung->regmap, COMBO_MD2_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1291 	regmap_write(samsung->regmap, DPHY_MD3_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1294 		regmap_write(samsung->regmap, COMBO_MD0_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1295 		regmap_write(samsung->regmap, COMBO_MD1_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1296 		regmap_write(samsung->regmap, COMBO_MD2_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1297 		regmap_write(samsung->regmap, DPHY_MD3_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1300 	val = 0;  in samsung_mipi_dphy_data_lane_timing_init()
1302 	 * Divide-by-2 Clock from Serial Clock. Use this when data rate is under  in samsung_mipi_dphy_data_lane_timing_init()
1303 	 * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock  in samsung_mipi_dphy_data_lane_timing_init()
1308 	val |= T_LPX(timing->lpx);  in samsung_mipi_dphy_data_lane_timing_init()
1310 	regmap_write(samsung->regmap, COMBO_MD0_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1311 	regmap_write(samsung->regmap, COMBO_MD1_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1312 	regmap_write(samsung->regmap, COMBO_MD2_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1313 	regmap_write(samsung->regmap, DPHY_MD3_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1315 	val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare);  in samsung_mipi_dphy_data_lane_timing_init()
1316 	regmap_write(samsung->regmap, COMBO_MD0_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1317 	regmap_write(samsung->regmap, COMBO_MD1_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1318 	regmap_write(samsung->regmap, COMBO_MD2_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1319 	regmap_write(samsung->regmap, DPHY_MD3_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1321 	val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->hs_trail_eot);  in samsung_mipi_dphy_data_lane_timing_init()
1322 	regmap_write(samsung->regmap, COMBO_MD0_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1323 	regmap_write(samsung->regmap, COMBO_MD1_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1324 	regmap_write(samsung->regmap, COMBO_MD2_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1325 	regmap_write(samsung->regmap, DPHY_MD3_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1327 	/* TTA-GET/TTA-GO Timing Counter register use default value */  in samsung_mipi_dphy_data_lane_timing_init()
1328 	val = T_TA_GET(0x3) | T_TA_GO(0x0);  in samsung_mipi_dphy_data_lane_timing_init()
1329 	regmap_write(samsung->regmap, COMBO_MD0_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1330 	regmap_write(samsung->regmap, COMBO_MD1_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1331 	regmap_write(samsung->regmap, COMBO_MD2_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1332 	regmap_write(samsung->regmap, DPHY_MD3_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1335 	regmap_write(samsung->regmap, COMBO_MD0_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1336 	regmap_write(samsung->regmap, COMBO_MD1_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1337 	regmap_write(samsung->regmap, COMBO_MD2_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1338 	regmap_write(samsung->regmap, DPHY_MD3_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1345 	reset_control_assert(samsung->m_phy_rst);  in samsung_mipi_dphy_power_on()
1352 	if (ret < 0)  in samsung_mipi_dphy_power_on()
1357 	reset_control_deassert(samsung->m_phy_rst);  in samsung_mipi_dphy_power_on()
1364 	return 0;  in samsung_mipi_dphy_power_on()
1371 	reset_control_assert(samsung->apb_rst);  in samsung_mipi_dcphy_power_on()
1373 	reset_control_deassert(samsung->apb_rst);  in samsung_mipi_dcphy_power_on()
1375 	switch (samsung->type) {  in samsung_mipi_dcphy_power_on()
1380 		return -EOPNOTSUPP;  in samsung_mipi_dcphy_power_on()
1383 	return 0;  in samsung_mipi_dcphy_power_on()
1390 	switch (samsung->type) {  in samsung_mipi_dcphy_power_off()
1396 		return -EOPNOTSUPP;  in samsung_mipi_dcphy_power_off()
1401 	return 0;  in samsung_mipi_dcphy_power_off()
1408 	unsigned long fin = div64_ul(clk_get_rate(samsung->ref_clk), MSEC_PER_SEC);  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1409 	u16 prediv = samsung->pll.prediv;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1410 	u16 fbdiv = samsung->pll.fbdiv;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1412 	u16 _mfr, best_mfr = 0;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1413 	u16 mr, _mrr, best_mrr = 0;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1418 	/*0 ≤ mfr ≤ 255 */  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1426 			/* 0 ≤ MR ≤ 5% */  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1439 		*mfr = best_mfr & 0xff;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1440 		*mrr = best_mrr & 0x3f;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1442 		dev_err(samsung->dev, "failed to calc ssc parameter mfr and mrr\n");  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1443 		return -EINVAL;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1446 	return 0;  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1453 	unsigned long prate = clk_get_rate(samsung->ref_clk);  in samsung_mipi_dcphy_pll_calc_rate()
1455 	u8 scaler = 0, mfr = 0, mrr = 0;  in samsung_mipi_dcphy_pll_calc_rate()
1456 	u16 fbdiv = 0;  in samsung_mipi_dcphy_pll_calc_rate()
1458 	int dsm = 0;  in samsung_mipi_dcphy_pll_calc_rate()
1465 	dev_dbg(samsung->dev, "%s: fin=%lu, req_rate=%llu\n",  in samsung_mipi_dcphy_pll_calc_rate()
1467 	dev_dbg(samsung->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n",  in samsung_mipi_dcphy_pll_calc_rate()
1470 	samsung->pll.prediv = prediv;  in samsung_mipi_dcphy_pll_calc_rate()
1471 	samsung->pll.fbdiv = fbdiv;  in samsung_mipi_dcphy_pll_calc_rate()
1472 	samsung->pll.dsm = dsm;  in samsung_mipi_dcphy_pll_calc_rate()
1473 	samsung->pll.scaler = scaler;  in samsung_mipi_dcphy_pll_calc_rate()
1474 	samsung->pll.rate = fout;  in samsung_mipi_dcphy_pll_calc_rate()
1484 			samsung->pll.ssc_en = true;  in samsung_mipi_dcphy_pll_calc_rate()
1485 			samsung->pll.mfr = mfr;  in samsung_mipi_dcphy_pll_calc_rate()
1486 			samsung->pll.mrr = mrr;  in samsung_mipi_dcphy_pll_calc_rate()
1495 	unsigned long long target_rate = opts->mipi_dphy.hs_clk_rate;  in samsung_mipi_dcphy_configure()
1497 	samsung->lanes = opts->mipi_dphy.lanes > 4 ? 4 : opts->mipi_dphy.lanes;  in samsung_mipi_dcphy_configure()
1500 	opts->mipi_dphy.hs_clk_rate = samsung->pll.rate;  in samsung_mipi_dcphy_configure()
1502 	return 0;  in samsung_mipi_dcphy_configure()
1509 	return pm_runtime_resume_and_get(samsung->dev);  in samsung_mipi_dcphy_init()
1516 	return pm_runtime_put(samsung->dev);  in samsung_mipi_dcphy_exit()
1533 	.max_register = 0x10000,
1541 	if (args->args_count != 1) {  in samsung_mipi_dcphy_xlate()
1543 		return ERR_PTR(-EINVAL);  in samsung_mipi_dcphy_xlate()
1546 	if (samsung->type != PHY_NONE && samsung->type != args->args[0])  in samsung_mipi_dcphy_xlate()
1548 			 args->args[0], samsung->type);  in samsung_mipi_dcphy_xlate()
1550 	samsung->type = args->args[0];  in samsung_mipi_dcphy_xlate()
1552 	return samsung->phy;  in samsung_mipi_dcphy_xlate()
1557 	struct device *dev = &pdev->dev;  in samsung_mipi_dcphy_probe()
1558 	struct device_node *np = dev->of_node;  in samsung_mipi_dcphy_probe()
1567 		return -ENOMEM;  in samsung_mipi_dcphy_probe()
1569 	samsung->dev = dev;  in samsung_mipi_dcphy_probe()
1570 	samsung->pdata = device_get_match_data(dev);  in samsung_mipi_dcphy_probe()
1573 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in samsung_mipi_dcphy_probe()
1578 	samsung->regmap = devm_regmap_init_mmio(dev, regs,  in samsung_mipi_dcphy_probe()
1580 	if (IS_ERR(samsung->regmap))  in samsung_mipi_dcphy_probe()
1581 		return dev_err_probe(dev, PTR_ERR(samsung->regmap), "Failed to init regmap\n");  in samsung_mipi_dcphy_probe()
1583 	samsung->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");  in samsung_mipi_dcphy_probe()
1584 	if (IS_ERR(samsung->grf_regmap))  in samsung_mipi_dcphy_probe()
1585 		return dev_err_probe(dev, PTR_ERR(samsung->grf_regmap),  in samsung_mipi_dcphy_probe()
1588 	samsung->ref_clk = devm_clk_get(dev, "ref");  in samsung_mipi_dcphy_probe()
1589 	if (IS_ERR(samsung->ref_clk))  in samsung_mipi_dcphy_probe()
1590 		return dev_err_probe(dev, PTR_ERR(samsung->ref_clk),  in samsung_mipi_dcphy_probe()
1593 	samsung->pclk = devm_clk_get(dev, "pclk");  in samsung_mipi_dcphy_probe()
1594 	if (IS_ERR(samsung->pclk))  in samsung_mipi_dcphy_probe()
1595 		return dev_err_probe(dev, PTR_ERR(samsung->pclk), "Failed to get pclk\n");  in samsung_mipi_dcphy_probe()
1597 	samsung->m_phy_rst = devm_reset_control_get(dev, "m_phy");  in samsung_mipi_dcphy_probe()
1598 	if (IS_ERR(samsung->m_phy_rst))  in samsung_mipi_dcphy_probe()
1599 		return dev_err_probe(dev, PTR_ERR(samsung->m_phy_rst),  in samsung_mipi_dcphy_probe()
1602 	samsung->s_phy_rst = devm_reset_control_get(dev, "s_phy");  in samsung_mipi_dcphy_probe()
1603 	if (IS_ERR(samsung->s_phy_rst))  in samsung_mipi_dcphy_probe()
1604 		return dev_err_probe(dev, PTR_ERR(samsung->s_phy_rst),  in samsung_mipi_dcphy_probe()
1607 	samsung->apb_rst = devm_reset_control_get(dev, "apb");  in samsung_mipi_dcphy_probe()
1608 	if (IS_ERR(samsung->apb_rst))  in samsung_mipi_dcphy_probe()
1609 		return dev_err_probe(dev, PTR_ERR(samsung->apb_rst),  in samsung_mipi_dcphy_probe()
1612 	samsung->grf_apb_rst = devm_reset_control_get(dev, "grf");  in samsung_mipi_dcphy_probe()
1613 	if (IS_ERR(samsung->grf_apb_rst))  in samsung_mipi_dcphy_probe()
1614 		return dev_err_probe(dev, PTR_ERR(samsung->grf_apb_rst),  in samsung_mipi_dcphy_probe()
1617 	samsung->phy = devm_phy_create(dev, NULL, &samsung_mipi_dcphy_ops);  in samsung_mipi_dcphy_probe()
1618 	if (IS_ERR(samsung->phy))  in samsung_mipi_dcphy_probe()
1619 		return dev_err_probe(dev, PTR_ERR(samsung->phy), "Failed to create MIPI DC-PHY\n");  in samsung_mipi_dcphy_probe()
1621 	phy_set_drvdata(samsung->phy, samsung);  in samsung_mipi_dcphy_probe()
1632 	return 0;  in samsung_mipi_dcphy_probe()
1639 	clk_disable_unprepare(samsung->ref_clk);  in samsung_mipi_dcphy_runtime_suspend()
1640 	clk_disable_unprepare(samsung->pclk);  in samsung_mipi_dcphy_runtime_suspend()
1642 	return 0;  in samsung_mipi_dcphy_runtime_suspend()
1650 	ret = clk_prepare_enable(samsung->pclk);  in samsung_mipi_dcphy_runtime_resume()
1652 		dev_err(samsung->dev, "Failed to enable pclk, %d\n", ret);  in samsung_mipi_dcphy_runtime_resume()
1656 	ret = clk_prepare_enable(samsung->ref_clk);  in samsung_mipi_dcphy_runtime_resume()
1658 		dev_err(samsung->dev, "Failed to enable reference clock, %d\n", ret);  in samsung_mipi_dcphy_runtime_resume()
1659 		clk_disable_unprepare(samsung->pclk);  in samsung_mipi_dcphy_runtime_resume()
1663 	return 0;  in samsung_mipi_dcphy_runtime_resume()
1697 		.compatible = "rockchip,rk3576-mipi-dcphy",
1700 		.compatible = "rockchip,rk3588-mipi-dcphy",
1709 		.name = "samsung-mipi-dcphy",
1717 MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");